參數(shù)資料
型號： DSP56301VF100
廠商： Freescale Semiconductor
文件頁數(shù)： 24/124頁
文件大小： 0K
描述： IC DSP 24BIT FIXED-POINT 252-BGA
產(chǎn)品變化通告： DSP56301 Discontinuation 12/Nov/2009
標(biāo)準(zhǔn)包裝： 60
系列： DSP563xx
類型： 定點
接口： 主機(jī)接口，SSI，SCI
時鐘速率： 100MHz
非易失內(nèi)存： ROM（9 kB）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 252-BGA
供應(yīng)商設(shè)備封裝： 252-MAPBGA（21x21）
包裝： 托盤
DSP56301 Technical Data, Rev. 10
1-8
Freescale Semiconductor
Signals/Connections
BB
Input/
Output
Input
Bus Busy
Indicates that the bus is active and must be asserted and deasserted
synchronous to CLKOUT. Only after BB is deasserted can the pending bus
master become the bus master (and then assert the signal again). The bus
master can keep BB asserted after ceasing bus activity, regardless of whether
BR is asserted or deasserted. This is called “bus parking” and allows the
current bus master to reuse the bus without re-arbitration until another device
requires the bus. BB is deasserted by an “active pull-up” method (that is, BB is
driven high and then released and held high by an external pull-up resistor).
BB requires an external pull-up resistor.
BL
Output
Driven high
(deasserted)
Bus Lock—BL is asserted at the start of an external divisible Read-Modify-
Write (RMW) bus cycle, remains asserted between the read and write cycles,
and is deasserted at the end of the write bus cycle. This provides an “early bus
start” signal for the bus controller. BL may be used to “resource lock” an
external multi-port memory for secure semaphore updates. Early deassertion
provides an “early bus end” signal useful for external bus control. If the
external bus is not used during an instruction cycle, BL remains deasserted
until the next external indivisible RMW cycle. The only instructions that assert
BL automatically are the BSET, CLR, and BCHG instructions when they are
used to modify external memory. An operation can also assert BL by setting
the BLH bit in the Bus Control Register.
CAS
Output
Tri-stated
Column Address Strobe
When the DSP is the bus master, DRAM uses CAS to strobe the column
address. Otherwise, if the Bus Mastership Enable (BME) bit in the DRAM
Control Register is cleared, the signal is tri-stated.
BCLK
Output
Tri-stated
Bus Clock
When the DSP is the bus master, BCLK is active when the OMR[ATE] is set.
When BCLK is active and synchronized to CLKOUT by the internal PLL, BCLK
precedes CLKOUT by one-fourth of a clock cycle.
BCLK
Output
Tri-stated
Bus Clock Not
When the DSP is the bus master, BCLK is the inverse of the BCLK signal.
Otherwise, the signal is tri-stated.
Table 1-8.
External Bus Control Signals (Continued)
Signal Name
Type
State During
Reset
Signal Description
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DSP56301VF80 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC MAP DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56301VF80B1 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSP56301VF80B1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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