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參數(shù)資料
| 型號： | BXM80526B700 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 700 MHz, MICROPROCESSOR, CPGA495 |
| 封裝： | MICRO, PGA2-495 |
| 文件頁數(shù)： | 28/85頁 |
| 文件大小： | 795K |
| 代理商： | BXM80526B700 |
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Mobile Intel Pentium III Processor in BGA2 and Micro-PGA2 Packages
at 850 MHz, 800 MHz, 750 MHz, 700 MHz, and Low-voltage 600 MHz
Datasheet
Order#-XXX
26
Table 19. TAP Signal AC Specifications
1
TJ = 0°C to 100°C; VCC = 1.10V ±80 mV; VCC = 1.35V ±100 mV or 1.60V ±115 mV; VCCT = 1.50V ±115 mV
Symbol
Parameter
Min
Max
Unit Figure
Notes
T30
TCK Frequency
—
16.67 MHz
T31
TCK Period
60
—
ns
Figure 6
T32
TCK High Time
25.0
ns
Figure 6
≥ 1.2V, Note 2
T33
TCK Low Time
25.0
ns
Figure 6
≤ 0.6V, Note 2
T34
TCK Rise Time
5.0
ns
Figure 6
(0.6V – 1.2V), Notes 2, 3
T35
TCK Fall Time
5.0
ns
Figure 6
(1.2V – 1.6V), Notes 2, 3
T36
TRST# Pulse Width
40.0
ns
Figure 13 Asynchronous, Note 2
T37
TDI, TMS Setup Time
5.0
ns
Figure 12 Note 4
T38
TDI, TMS Hold Time
14.0
ns
Figure 12 Note 4
T39
TDO Valid Delay
1.0
10.0
ns
Figure 12 Notes 5, 6
T40
TDO Float Delay
25.0
ns
Figure 12 Notes 2, 5, 6
T41
All Non-Test Outputs Valid Delay
2.0
25.0
ns
Figure 12 Notes 5, 7, 8
T42
All Non-Test Outputs Float Delay
25.0
ns
Figure 12 Notes 2, 5, 7, 8
T43
All Non-Test Inputs Setup Time
5.0
ns
Figure 12 Notes 4, 7, 8
T44
All Non-Test Inputs Hold Time
13.0
ns
Figure 12 Notes 4, 7, 8
NOTES:
1.
All AC timings for TAP signals are referenced to the TCK rising edge at 0.75V. All TAP and CMOS signals are referenced
at 0.75V.
2.
Not 100% tested. Specified by design/characterization.
3.
1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16 MHz.
4.
Referenced to TCK rising edge.
5.
Referenced to TCK falling edge.
6.
Valid delay timing for this signal is specified into 150
terminated to 1.5V and 0 pF of external load. For real system
timings these specifications must be derated for external capacitance at 105 ps/pF.
7.
Non-Test Outputs and Inputs are the normal output or input signals (except TCK, TRST#, TDI, TDO, and TMS). These
timings correspond to the response of these signals due to boundary scan operations.
8.
During Debug Port operation use the normal specified timings rather than the TAP signal timings.
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