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參數(shù)資料
| 型號： | BXM80526B700 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 700 MHz, MICROPROCESSOR, CPGA495 |
| 封裝： | MICRO, PGA2-495 |
| 文件頁數(shù)： | 26/85頁 |
| 文件大?。?/td> | 795K |
| 代理商： | BXM80526B700 |
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Mobile Intel Pentium III Processor in BGA2 and Micro-PGA2 Packages
at 850 MHz, 800 MHz, 750 MHz, 700 MHz, and Low-voltage 600 MHz
Datasheet
Order#-XXX
24
Table 15. GTL+ Signal Groups AC Specifications
1
RTT =
56 internally terminated to V
CCT; VREF =
2/
3VCCT; load = 0 pF;
TJ = 0°C to 100°C; VCC = 1.10V ±80 mV; VCC = 1.35V ±100 mV or 1.60V ±115 mV; VCCT = 1.50V ±115 mV
Symbol
Parameter
Min
Max
Unit
Figure
Notes
T7
GTL+ Output Valid Delay
0.2
2.7
ns
Figure 8
T8
GTL+ Input Setup Time
1.2
ns
Figure 9
Notes 2, 3
T9
GTL+ Input Hold Time
0.80
ns
Figure 9
Note 4
T10
RESET# Pulse Width
1ms
Figure 10,
Figure 11
Note 5
NOTES:
1.
All AC timings for GTL+ signals are referenced to the BCLK rising edge at 1.25V. All GTL+ signals are referenced at
VREF.
2.
RESET# can be asserted (active) asynchronously, but must be de-asserted synchronously.
3.
Specification is for a minimum 0.40V swing.
4.
Specification is for a maximum 1.0V swing.
5.
After VCC, VCCT, and BCLK become stable and PWRGOOD is asserted.
Table 16. CMOS and Open-drain Signal Groups AC Specifications
1, 2
TJ = 0°C to 100°C; VCC = 1.10V ±80 mV; VCC = 1.35V ±100 mV or 1.60V ±115 mV; VCCT = 1.50V ±115 mV
Symbol Parameter
Min Max Unit
Figure
Notes
T14
1.5V Input Pulse Width, except PWRGOOD and
LINT[1:0]
2
BCLKs Figure 8
Active and
Inactive states
T14B
LINT[1:0] Input Pulse Width
6
BCLKs Figure 8
Note 3
T15
PWRGOOD Inactive Pulse Width
10
BCLKs Figure 11 Notes 4, 5
NOTES:
1.
All AC timings for CMOS and Open-drain signals are referenced to the BCLK rising edge at 1.25V. All CMOS and Open-
drain signals are referenced at 0.75V.
2.
Minimum output pulse width on CMOS outputs is 2 BCLKs.
3.
This specification only applies when the APIC is enabled and the LINT1 or LINT0 signal is configured as an edge
triggered interrupt with fixed delivery, otherwise specification T14 applies.
4.
When driven inactive, or after VCC, VCCT and BCLK become stable. PWRGOOD must remain below VIL25,max from Table 12
until all the voltage planes meet the voltage tolerance specifications in Table 9 and BCLK has met the BCLK AC
specifications in Table 13 for at least 10 clock cycles. PWRGOOD must rise glitch-free and monotonically to 2.5V.
5.
If the BCLK Settling Time specification (T60) can be guaranteed at power-on reset then the PWRGOOD Inactive Pulse
Width specification (T15) is waived and BCLK may start after PWRGOOD is asserted. PWRGOOD must still remain
below VIL25,max until all the voltage planes meet the voltage tolerance specifications.
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