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參數(shù)資料
| 型號： | BXM80526B700 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 700 MHz, MICROPROCESSOR, CPGA495 |
| 封裝： | MICRO, PGA2-495 |
| 文件頁數(shù)： | 21/85頁 |
| 文件大?。?/td> | 795K |
| 代理商： | BXM80526B700 |
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Mobile Intel Pentium III Processor in BGA2 and Micro-PGA2 Packages
at 850 MHz, 800 MHz, 750 MHz, 700 MHz, and Low-voltage 600 MHz
Datasheet
Order#-XXX
20
7.
VCCx must be within this range under all operating conditions, including maximum current transients. VCCx must return
to within the static voltage specification, VCCx,DC, within 100 s after a transient event. The average of VCCx over time
must not exceed 1.65V, as an arbitrarily large time span may be used for this average.
8.
Voltages are measured at the processor package pin for the Micro-PGA2 part and at the package ball on the BGA2 part.
The signals on the mobile Pentium III processor system bus are included in the GTL+ signal
group. These signals are specified to be terminated to VCC. The DC specifications for these signals
are listed in
Table 10 and the termination and reference voltage specifications for these signals are listed in
Mobile Pentium III Processor GTL+ System Bus Layout Guideline for full details of system VCCT
and VREF requirements. The CMOS, Open-drain, and TAP signals are designed to interface at
1.5V levels to allow connection to other devices. BCLK and PICCLK are designed to receive a
2.5-V clock signal. The DC specifications for these signals are listed Table 12.
Table 10. GTL+ Signal Group DC Specifications
TJ = 0°C to 100°C; VCC = 1.10V ±80 mV; VCC = 1.35V ±100 mV or 1.60V ±115 mV; VCCT = 1.50V ±115 mV
Symbol
Parameter
Min
Max
Unit
Notes
VOH
Output High Voltage
—
V
See VCCT,max in
RON
Output Low Drive Strength
16.67
IL
Leakage Current for Inputs, Outputs and I/Os
±100
A
Note 1
NOTE:
(0
≤ VIN/OUT ≤ VCCT).
Table 11. GTL+ Bus DC Specifications
TJ = 0°C to 100°C; VCC = 1.10V ±80 mV; VCC = 1.35V ±100 mV or 1.60V ±115 mV; VCCT = 1.50V ±115 mV
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VCCT
Bus Termination Voltage
1.385
1.5
1.615
V
Note 1
VREF
Input Reference Voltage
2/
3VCCT – 2%
2/
3VCCT
2/
3VCCT + 2%
V
±2%, Note 2
RTT
Bus Termination Strength
50
56
65
On-die RTT,
Note 3
NOTES:
1.
For simulation use 1.50V ±10%. For typical simulation conditions use VCCTmin (1.5V –10%).
2.
VREF should be created from VCCT by a voltage divider.
3.
The RESET# signal does not have an on-die RTT. It requires an off-die 56.2
±1% terminating resistor connected to
VCCT.
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