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參數(shù)資料
| 型號： | BXM80526B700 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 700 MHz, MICROPROCESSOR, CPGA495 |
| 封裝： | MICRO, PGA2-495 |
| 文件頁數(shù)： | 13/85頁 |
| 文件大?。?/td> | 795K |
| 代理商： | BXM80526B700 |
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Mobile Intel Pentium III Processor in BGA2 and Micro-PGA2 Packages
at 850 MHz, 800 MHz, 750 MHz, 700 MHz, and Low-voltage 600 MHz
Datasheet
Order#-XXX
12
3 Electrical Specifications
3.1 Processor System Signals
Table 6 lists the processor system signals by type. All GTL+ signals are synchronous with the
BCLK signal. All TAP signals are synchronous with the TCK signal except TRST#. All CMOS
input signals can be applied asynchronously.
Table 6. System Signal Groups
Group Name
Signals
GTL+ Input
BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
GTL+ Output
PRDY#
GTL+ I/O
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#,
BPM[1:0]#, BREQ0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#,
LOCK#, REQ[4:0]#, RP#
1.5V CMOS Input
2
A20M#, FLUSH#, GHI#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#,
SLP#, SMI#, STPCLK#
2.5V CMOS Input
1, 3
PWRGOOD
1.5V Open Drain Output
2
FERR#, IERR#
3.3V CMOS Input
4
BSEL[1:0]
Clock
3
BCLK
APIC Clock
3
PICCLK
APIC I/O
2
PICD[1:0]
Thermal Diode
THERMDA, THERMDC
TAP Input
2
TCK, TDI, TMS, TRST#
TAP Output
2
TDO
Power/Other
5
CLKREF, CMOSREF, EDGECTRLP, NC, PLL1, PLL2, RSVD, RTTIMPEDP,
TESTHI, TESTLO[2:1], VCC, VCCT, VID[4:0], VREF, VSS
NOTES:
1.
See Section 8.1 for information on the PWRGOOD signal.
2.
These signals are tolerant to 1.5V only. See Table 7 for the recommended pull-up resistor.
3.
These signals are tolerant to 2.5V only. See Table 7 for the recommended pull-up resistor.
4.
These signals are tolerant to 3.3V only. See Table 7 for the recommended pull-up resistor.
5.
VCC is the power supply for the core logic.
PLL1 and PLL2 are the power supply for the PLL analog section.
VCCT is the power supply for the system bus buffers.
VREF is the voltage reference for the GTL+ input buffers.
VSS is system ground.
The CMOS, APIC, and TAP inputs can be driven from ground to 1.5V. BCLK, PICCLK, and
PWRGOOD can be driven from ground to 2.5V. The APIC data and TAP outputs are Open-drain
and should be pulled up to 1.5V using resistors with the values shown in Table 7. If Open-drain
drivers are used for input signals, then they should also be pulled up to the appropriate voltage
using resistors with the values shown in Table 7.
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