參數(shù)資料
型號(hào)： BXM80526B700
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 700 MHz, MICROPROCESSOR, CPGA495
封裝： MICRO, PGA2-495
文件頁(yè)數(shù)： 11/85頁(yè)
文件大?。?/td> 795K
代理商： BXM80526B700
Mobile Intel Pentium III Processor in BGA2 and Micro-PGA2 Packages
at 850 MHz, 800 MHz, 750 MHz, 700 MHz, and Low-voltage 600 MHz
Order#-XXX
Datasheet
11
processor will start in the lower of its two core frequencies, the “Battery Optimized” mode. An
operating mode transition to the high core frequency can be made by putting the processor into the
Deep Sleep state, raising the core voltage, setting GHI# low, and returning to the Normal state.
This puts the processor into the “Maximum performance” mode. A transitioning back to the low-
core frequency can be made by reversing these steps. Refer to the Geyserville Hardware Technical
Specification (reference numberSC-2375) and the Geyserville Software Architecture Specification
(reference number SC-2364) for more information on Intel SpeedStep technology.
2.3 GTL+ Signals
The mobile Pentium III processor system bus signals use a variation of the low-voltage swing GTL
signaling technology. The mobile Pentium III processor system bus specification is similar to the
Pentium II processor system bus specification, which is a version of GTL with enhanced noise
margins and less ringing.
The GTL+ system bus depends on incident wave switching and uses flight time for timing
calculations of the GTL+ signals, as opposed to capacitive derating. Analog signal simulation of
the system bus including trace lengths is highly recommended. Contact your field sales
representative to receive the IBIS models for the mobile Pentium III processor.
The GTL+ system bus of the Pentium II processor was designed to support high-speed data
transfers with multiple loads on a long bus that behaves like a transmission line. However, in
mobile systems the system bus only has two loads (the processor and the chipset) and the bus
traces are short. It is possible to change the layout and termination of the system bus to take
advantage of the mobile environment using the same GTL+ I/O buffers. In mobile systems the
GTL+ system bus is terminated at one end only. This termination is provided on the processor
core (except for the RESET# signal). Refer to the Mobile Coppermine Processor GTL+ System
Bus Layout Guideline for details on laying out the GTL+ system bus.
2.4 Mobile Pentium III Processor CPUID
The CPUID instruction does not distinguish between the Pentium III processor and the mobile
Pentium III processor. After a power-on RESET or when the CPUID version information is
loaded, the EAX register contains the values shown in Table 4. After the L2 cache is initialized,
the CPUID cache/TLB descriptors will be the values shown in Table 5.
Table 4. Mobile Pentium III Processor CPUID
EAX[31:0]
EBX[7:0]
Reserved [31:14]
Type [13:12] Family [11:8]
Model [7:4] Stepping [3:0]
Brand ID
X0
6
8
X
02
Table 5. Mobile Pentium III Processor CPUID Cache and TLB Descriptors
Cache and TLB Descriptors
01H, 02H, 03H, 04H, 08H, 0CH, 82H
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