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參數(shù)資料
| 型號： | BX80557E2140 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, PBGA775 |
| 封裝： | LGA-775 |
| 文件頁數(shù)： | 96/107頁 |
| 文件大?。?/td> | 1474K |
| 代理商： | BX80557E2140 |
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Datasheet
89
Features
6.2.2.1
HALT Powerdown State
HALT is a low power state entered when all the processor cores have executed the HALT
or MWAIT instructions. When one of the processor cores executes the HALT instruction,
that processor core is halted, however, the other processor continues normal operation.
The processor will transition to the Normal state upon the occurrence of SMI#, INIT#,
or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize
itself.
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT Power Down state. See the Intel Architecture Software
Developer's Manual, Volume III: System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the HALT powerdown
state. When the system de-asserts the STPCLK# interrupt, the processor will return
execution to the HALT state.
While in HALT powerdown state, the processor will process bus snoops.
6.2.2.2
Extended HALT Powerdown State
Extended HALT is a low power state entered when all processor cores have executed
the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
When one of the processor cores executes the HALT instruction, that logical processor
is halted; however, the other processor continues normal operation. The Extended
HALT powerdown state must be enabled via the BIOS for the processor to remain
within its specification.
The processor will automatically transition to a lower frequency and voltage operating
point before entering the Extended HALT state. Note that the processor FSB frequency
is not altered; only the internal core frequency is changed. When entering the low
power state, the processor will first switch to the lower bus ratio and then transition to
the lower VID.
While in Extended HALT state, the processor will process bus snoops.
The processor exits the Extended HALT state when a break event occurs. When the
processor exits the Extended HALT state, it will resume operation at the lower
frequency, transition the VID to the original value, and then change the bus ratio back
to the original value.
6.2.3
Stop Grant and Extended Stop Grant States
The processor supports the Stop Grant and Extended Stop Grant states. The Extended
Stop Grant state is a feature that must be configured and enabled via the BIOS. Refer
to the following sections for details about the Stop Grant and Extended Stop Grant
states.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX80557E2160 S LA8Z | 制造商:Intel 功能描述: |
| BX80557E4400 | 制造商:Intel 功能描述:MPU Core?2 Duo Processor E4400 65nm 2GHz 775-Pin FCLGA6 |
| BX80557E4500 S LA95 | 制造商:Intel 功能描述:MPU Core?2 Duo Processor E4500 65nm 2.2GHz 775-Pin FCLGA6 |
| BX80557E4600 S LA94 | 制造商:Intel 功能描述:MPU Core?2 Duo Processor E4600 65nm 2.4GHz 775-Pin FCLGA6 |
| BX80557E6300 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intel 功能描述: |
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