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參數(shù)資料
| 型號(hào)： | BX80557E2140 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, PBGA775 |
| 封裝： | LGA-775 |
| 文件頁數(shù)： | 70/107頁 |
| 文件大小： | 1474K |
| 代理商： | BX80557E2140 |
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Land Listing and Signal Descriptions
Datasheet
65
BPM[5:0]#
Input/
Output
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor which indicate
the status of breakpoints and programmable counters used for
monitoring processor performance. BPM[5:0]# should connect the
appropriate pins/lands of all processor FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port.
PRDY# is a processor output used by debug tools to determine
processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP
port. PREQ# is used by debug tools to request debug operation of
the processor.
These signals do not have on-die termination. Refer to Section 2.6.2
for termination requirements.
BPRI#
Input
BPRI# (Bus Priority Request) is used to arbitrate for ownership of
the processor FSB. It must connect the appropriate pins/lands of all
processor FSB agents. Observing BPRI# active (as asserted by the
priority agent) causes all other agents to stop issuing new requests,
unless such requests are part of an ongoing locked operation. The
priority agent keeps BPRI# asserted until all of its requests are
completed, then releases the bus by de-asserting BPRI#.
BR0#
Input/
Output
BR0# drives the BREQ0# signal in the system and is used by the
processor to request the bus. During power-on configuration this
signal is sampled to determine the agent ID = 0.
This signal does not have on-die termination and must be
terminated.
BSEL[2:0]
Output
The BCLK[1:0] frequency select signals BSEL[2:0] are used to select
the processor input clock frequency. Table 16 defines the possible
combinations of the signals and the frequency associated with each
combination. The required frequency is determined by the processor,
chipset and clock synthesizer. All agents must operate at the same
frequency. For more information about these signals, including
termination recommendations refer to Section 2.8.2.
COMP8
COMP[3:0]
Analog
COMP[3:0] and COMP8 must be terminated to VSS on the system
board using precision resistors.
Table 25.
Signal Description (Sheet 2 of 9)
Name
Type
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX80557E2160 S LA8Z | 制造商:Intel 功能描述: |
| BX80557E4400 | 制造商:Intel 功能描述:MPU Core?2 Duo Processor E4400 65nm 2GHz 775-Pin FCLGA6 |
| BX80557E4500 S LA95 | 制造商:Intel 功能描述:MPU Core?2 Duo Processor E4500 65nm 2.2GHz 775-Pin FCLGA6 |
| BX80557E4600 S LA94 | 制造商:Intel 功能描述:MPU Core?2 Duo Processor E4600 65nm 2.4GHz 775-Pin FCLGA6 |
| BX80557E6300 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intel 功能描述: |
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