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ASIX ELECTRONICS CORPORATION
50
AX88796 L 3-in-1 Local Bus Fast Ethernet Controller
5.2.17 MR31 –Device-Specific Register 4 (Quick Status) Bit Descriptions
FIELD
TYPE
31.15 (ERROR)
R
Receiver Error.
When this bit is a 1, it indicates that a receive error has been
detected. This bit is valid in 100Mbits/s only. This bit will remain set until
cleared by reading the register. Default is a 0.
31.14
(RXERR_ST)/(LINK_ST
AT_CHANGE)
100Mbits/s only. This bit will remain set until cleared by reading the register.
Default is 0.
Link Status Change.
When bit [31.7] is set to a 1, this bit is redefined to become
the LINK_STAT_CHANGE bit and goes high whenever there is a change in link
status (bit [31.11] changes state)
31.13 (REM_FLT)
R
Remote Fault.
When this bit is a 1, it indicates a remote fault has been detected.
This bit will remain set until cleared by reading the register. Default is a 0.
31.12
(UNLOCKED)/(JABBE
R)
in 10Mbits/s mode, it indicates a jabber condition has been detected. This bit will
remain set until cleared by reading the register.
31.11 (LSTAT_OK)
R
Link Status.
When this bit is a 1, it indicates a valid link has been established.
This bit has a latching low function: a link failure will cause the bit to clear and
stay cleared until it has been read via the management interface.
31.10 (PAUSE)
R
Link Partner Pause.
When this bit is set to a 1, it indicates that the
LU3X54FTL wishes to exchange flow control information.
31.9 (SPEED100)
R
Link Speed.
When this bit is set to a 1, it indicates that the link has negotiated to
100Mbits/s. When this bit is a 0, it indicates that the link is operating at
10Mbits/s.
31.8 (FULL_DUP)
R
Duplex Mode.
When this bit is set to a 1, it indicates that the link has negotiated
to full-duplex mode. When this bit is a 0, it indicates that the link has negotiated
to half-duplex mode.
31.7 (INT_CONF)
R/W
Interrupt Configuration.
When this bit is set to a 0, it defines bit [31.14] to be
the RXERR_ST bit and the interrupt pin (MASK_STAT_INT) goes high
whenever any of bits [31.15:12] go high, or bit [31.11] goes low. When this bit is
set high, it redefines bit [31.14] to become the LINK_STAT_CHANGE bit, and
the interrupt pin (MASK_STAT_INT) goes high only when the link status
changes (bit [31.14] goes high). This bit defaults to 0.
31.6 (INT_MASK)
R/W
Interrupt Mask.
When set high, no interrupt is generated by this channel under
any condition. When set low, interrupts are generated according to bit [31.7].
31.5:3
(LOW_AUTO__STATE)
autonegotiation state reached since the last register read, in the priority order
defined below:
000: Autonegotiation enable.
001: Transmit disables or ability detects.
010: Link status check.
011: Acknowledge detects.
100: Complete acknowledges.
101: FLP link good check.
110: Next page wait.
111: FLP link good.
31.2:0
(HI_AUTO_STATE)
autonegotiation state reached since the last register read, as defined above for bit
[31.5:3].
DESCRIPTION
R
False Carrier.
When bit [31.7] is set to 0 and this bit is a 1, it indicates that the
carrier detect state machine has found a false carrier. This bit is valid in
R
Unlocked/Jabber.
If this bit is set when operating in 100Mbits/s mode, it
indicates that the TX descrambler has lost lock. If this bit is set when operating
R
Lowest Autonegotiation State.
These 3 bits report the state of the lowest
R
Highest Autonegotiation State.
These 3 bits report the state of the highest