參數(shù)資料
型號: AX88796
廠商: Electronic Theatre Controls, Inc.
英文描述: 3-in-1 Local Bus Fast Ethernet Controller
中文描述: 3合1本地總線快速以太網(wǎng)控制器
文件頁數(shù): 32/71頁
文件大?。?/td> 931K
代理商: AX88796
ASIX ELECTRONICS CORPORATION
32
AX88796 L 3-in-1 Local Bus Fast Ethernet Controller
5.0 Registers Operation
5.1 MAC Core Registers
All registers of MAC Core are 8-bit wide and mapped into pages which are selected by PS (Page Select) in
the Command Register.
PAGE 0 (PS1=0,PS0=0)
OFFSET
READ
00H
Command Register
( CR )
01H
Page Start Register
( PSTART )
02H
Page Stop Register
( PSTOP )
03H
Boundary Pointer
( BNRY )
04H
Transmit Status Register
( TSR )
05H
Number of Collisions Register
( NCR )
06H
Current Page Register
( CPR )
07H
Interrupt Status Register
( ISR )
08H
Current Remote DMA Address 0
( CRDA0 )
09H
Current Remote DMA Address 1
( CRDA1 )
0AH
Reserved
WRITE
Command Register
( CR )
Page Start Register
( PSTART )
Page Stop Register
( PSTOP )
Boundary Pointer
( BNRY )
Transmit Page Start Address
( TPSR )
Transmit Byte Count Register 0
( TBCR0 )
Transmit Byte Count Register 1
( TBCR1 )
Interrupt Status Register
( ISR )
Remote Start Address Register 0
( RSAR0 )
Remote Start Address Register 1
( RSAR1 )
Remote Byte Count 0
( RBCR0 )
Remote Byte Count 1
( RBCR1 )
Receive Configuration Register
( RCR )
Transmit Configuration Register ( TCR )
Data Configuration Register
( DCR )
Interrupt Mask Register
( IMR )
Data Port
IFGS1
IFGS2
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
GPOC
Standard Printer Port (SPP)
Reserved
Reserved
0BH
Reserved
0CH
Receive Status Register
( RSR )
Reserved
Reserved
0DH
0EH
0FH
Reserved
10H, 11H
12H
13H
14H
15H
16H
17H
18H - 1AH
1BH - 1EH
1FH
Data Port
IFGS1
IFGS2
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
GPI
Standard Printer Port (SPP)
Reserved
Reset
Tab - 12 Page 0 of MAC Core Registers Mapping
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