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參數(shù)資料
| 型號： | AX88796 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3-in-1 Local Bus Fast Ethernet Controller |
| 中文描述： | 3合1本地總線快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 23/71頁 |
| 文件大小： | 931K |
| 代理商： | AX88796 |
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ASIX ELECTRONICS CORPORATION
23
AX88796 L 3-in-1 Local Bus Fast Ethernet Controller
INITIALIZATION OF THE BUFFER RING
Two static registers and two working registers control the operation of the Buffer Ring. These are the Page Start
Register, Page Stop Register (both described previously), the Current Page Register and the Boundary Pointer
Register. The Current Page Register points to the first buffer used to store a packet and is used to restore the
DMA for writing status to the Buffer Ring or for restoring the DMA address in the event of a Runt packet, a
CRC, or Frame Alignment error. The Boundary Register points to the first packet in the Ring not yet read by the
host. If the local DMA address ever reaches the Boundary, reception is aborted. The Boundary Pointer is also
used to initialize the Remote DMA for removing a packet and is advanced when a packet is removed. A simple
analogy to remember the function of these registers is that the Current Page Register acts as a Write Pointer and
the Boundary Pointer acts as a Read Pointer.
Buffer #1
Buffer #2
Buffer #3
…
…
…
…
Buffer #n
Physical Memory Map
Logic Receive Buffer Ring
Fig - 9 Receive Buffer Ring At Initialization
BEGINNING OF RECEPTION
When the first packet begins arriving the AX88796 and begins storing the packet at the location pointed to by the
Current Page Register. An offset of 4 bytes is reserved in this first buffer to allow room for storing receive status
corresponding to this packet.
LINKING RECEIVE BUFFER PAGES
If the length of the packet exhausts the first 256 bytes buffer, the DMA performs a forward link to the next buffer
to store the remainder of the packet. For a maximal length packet the buffer logic will link six buffers to store the
entire packet. Buffers cannot be skipped when linking, a packet will always be stored in contiguous buffers.
Before the next buffer can be linked, the Buffer Management Logic performs two comparisons. The first
comparison tests for equality between the DMA address of the next buffer and the contents of the Page Stop
Register. If the buffer address equals the Page Stop Register, the buffer management logic will restore the DMA
to the first buffer in the Receive Buffer Ring value programmed in the Page Start Address Register. The second
comparison test for equality between the DMA address of the next buffer address and the contents of the
Boundary Pointer Register. If the two values are equal the reception is aborted. The Boundary Pointer Register
can be used to protect against overwriting any area in the receive buffer ring that has not yet been read. When
linking buffers, buffer management will never cross this pointer, effectively avoiding any overwrites. If the
4000h
8000h
Page Start
Page Stop
1
2
3
4
…
n-2
n-1
n
Boundary Page
Current Page
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AX88796L | 3-in-1 Local Bus Fast Ethernet Controller |
| AY3-8910 | PROGRAMMABLE SOUND GENERATOR |
| AY-3-8910 | PROGRAMMABLE SOUND GENERATOR |
| AY-3-8912 | PROGRAMMABLE SOUND GENERATOR |
| AY-3-8913 | PROGRAMMABLE SOUND GENERATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX88796ALF | 制造商:ASIX 功能描述:10/100 MAC,COMMERCIAL 128PIN |
| AX88796BLF | 制造商:Asix Electronics 功能描述:IEEE802.3 / IEEE802.3u LAN standard Ethernet 3.3V 64LQFP Tray 制造商:ASIX 功能描述:10/100 MAC,COMMERCIAL 64PIN |
| AX88796BLI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High-Performance Non-PCI Single-Chip 8/16 bit 10/100M Fast Ethernet Controller |
| AX88796C | 制造商:ASIX 制造商全稱:ASIX 功能描述:Low-Power SPI or Non-PCI Ethernet Controller |
| AX88796CLF | 制造商:ASIX Electronics Corporation 功能描述: |
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