ASIX ELECTRONICS CORPORATION
4
AX88796 L 3-in-1 Local Bus Fast Ethernet Controller
FIGURES
F
IG
- 1 AX88796 B
LOCK
D
IAGRAM
............................................................................................................................. 5
F
IG
- 2 AX88796 P
IN
C
ONNECTION
D
IAGRAM
.............................................................................................................. 6
F
IG
- 3 AX88796 P
IN
C
ONNECTION
D
IAGRAM WITH
SPP P
ORT
O
PTION
......................................................................... 7
F
IG
- 4 AX88796 P
IN
C
ONNECTION
D
IAGRAM FOR
ISA B
US
M
ODE
............................................................................... 8
F
IG
- 5 AX88796 P
IN
C
ONNECTION
D
IAGRAM FOR
80
X
86 M
ODE
.................................................................................. 9
F
IG
- 6 AX88796 P
IN
C
ONNECTION
D
IAGRAM FOR
MC68K M
ODE
.............................................................................. 10
F
IG
- 7 AX88796 P
IN
C
ONNECTION
D
IAGRAM FOR
MCS-51 M
ODE
............................................................................. 11
F
IG
- 8 R
ECEIVE
B
UFFER
R
ING
.................................................................................................................................... 22
F
IG
- 9 R
ECEIVE
B
UFFER
R
ING
A
T
I
NITIALIZATION
...................................................................................................... 23
TABLES
T
AB
- 1 L
OCAL
CPU
BUS INTERFACE SIGNALS GROUP
.................................................................................................. 12
T
AB
- 2 10/100M
BPS
T
WISTED
-P
AIR
I
NTERFACES PINS GROUP
..................................................................................... 13
T
AB
- 3 B
UILT
-
IN
PHY LED
INDICATOR PINS GROUP
.................................................................................................. 13
T
AB
- 4 EEPROM
BUS INTERFACE SIGNALS GROUP
..................................................................................................... 14
T
AB
- 5 MII
INTERFACE SIGNALS GROUP
..................................................................................................................... 14
T
AB
- 6 S
TANDARD
P
RINTER
P
ORT
I
NTERFACE PINS GROUP
......................................................................................... 15
T
AB
- 7 G
ENERAL
P
URPOSES
I/O
PINS GROUP
.............................................................................................................. 15
T
AB
- 8 M
ISCELLANEOUS PINS GROUP
......................................................................................................................... 17
T
AB
- 9 P
OWER ON
C
ONFIGURATION
S
ETUP
T
ABLE
..................................................................................................... 17
T
AB
- 10 I/O A
DDRESS
M
APPING
............................................................................................................................... 18
T
AB
- 11 L
OCAL
M
EMORY
M
APPING
.......................................................................................................................... 18
T
AB
- 12 P
AGE
0
OF
MAC C
ORE
R
EGISTERS
M
APPING
................................................................................................ 32
T
AB
- 13 P
AGE
1
OF
MAC C
ORE
R
EGISTERS
M
APPING
................................................................................................ 33
T
AB
-
14 T
HE
E
MBEDDED
PHY R
EGISTERS
................................................................................................................. 40
T
AB
- 15 MII M
ANAGEMENT
F
RAME
F
ORMAT
............................................................................................................ 53
T
AB
- 16 MII M
ANAGEMENT
F
RAMES
-
FIELD
D
ESCRIPTION
......................................................................................... 53