參數(shù)資料
型號(hào)： AX88796
廠商： Electronic Theatre Controls, Inc.
英文描述： 3-in-1 Local Bus Fast Ethernet Controller
中文描述： 3合1本地總線快速以太網(wǎng)控制器
文件頁(yè)數(shù)： 2/71頁(yè)
文件大?。?/td> 931K
代理商： AX88796
ASIX ELECTRONICS CORPORATION
2
AX88796 L 3-in-1 Local Bus Fast Ethernet Controller
CONTENTS
1.0 INTRODUCTION .............................................................................................................................................. 5
1.1 G
ENERAL
D
ESCRIPTION
:..................................................................................................................................... 5
1.2 AX88796 B
LOCK
D
IAGRAM
:.............................................................................................................................. 5
1.3
A
AX88796 P
IN
C
ONNECTION
D
IAGRAM
.............................................................................................................. 6
1.3
B
AX88796 P
IN
C
ONNECTION
D
IAGRAM WITH
SPP P
ORT
O
PTION
........................................................................ 7
1.3.1 AX88796 Pin Connection Diagram for ISA Bus Mode................................................................................ 8
1.3.2 AX88796 Pin Connection Diagram for 80x86 Mode................................................................................... 9
1.3.3 AX88796 Pin Connection Diagram for MC68K Mode.............................................................................. 10
1.3.4 AX88796 Pin Connection Diagram for MCS-51 Mode ............................................................................. 11
2.0 SIGNAL DESCRIPTION................................................................................................................................. 12
2.1 L
OCAL
CPU B
US
I
NTERFACE
S
IGNALS
G
ROUP
................................................................................................... 12
2.2 10/100M
BPS
T
WISTED
-P
AIR
I
NTERFACE PINS GROUP
......................................................................................... 13
2.3 B
UILT
-
IN
PHY LED
INDICATOR PINS GROUP
..................................................................................................... 13
2.4 EEPROM S
IGNALS
G
ROUP
.............................................................................................................................. 14
2.5 MII
INTERFACE SIGNALS GROUP
(O
PTIONAL
) ..................................................................................................... 14
2.6 S
TANDARD
P
RINTER
P
ORT
(SPP) I
NTERFACE PINS GROUP
(O
PTIONAL
)................................................................ 15
2.7 G
ENERAL
P
URPOSE
I/O
PINS GROUP
........................................................................................... 15
2.8 M
ISCELLANEOUS PINS GROUP
............................................................................................................................ 16
2.9 P
OWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE
..................... 17
3.0 MEMORY AND I/O MAPPING...................................................................................................................... 18
3.1 EEPROM M
EMORY
M
APPING
.......................................................................................................................... 18
3.2 I/O M
APPING
................................................................................................................................................... 18
3.3 SRAM M
EMORY
M
APPING
.............................................................................................................................. 18
4.0 BASIC OPERATION...................................................................................................................................... 19
4.1 R
ECEIVER
F
ILTERING
....................................................................................................................................... 19
4.1.1 Unicast Address Match Filter................................................................................................................... 19
4.1.2 Multicast Address Match Filter................................................................................................................ 19
4.1.3 Broadcast Address Match Filter............................................................................................................... 20
4.1.4 Aggregate Address Filter with Receive Configuration Setup..................................................................... 20
4.2 B
UFFER
M
ANAGEMENT
O
PERATION
.................................................................................................................. 22
4.2.1 Packet Reception ..................................................................................................................................... 22
4.2.2 Packet Transmision.................................................................................................................................. 25
4.2.3 Filling Packet to Transmit Buffer (Host fill data to memory).................................................................... 27
4.2.4 Removing Packets from the Ring (Host read data from memory).............................................................. 28
4.2.5 Other Useful Operations.......................................................................................................................... 31
5.0 REGISTERS OPERATION............................................................................................................................. 32
5.1 MAC C
ORE
R
EGISTERS
.................................................................................................................................... 32
5.1.1 Command Register (CR) Offset 00H (Read/Write)................................................................................... 34
5.1.2 Interrupt Status Register (ISR) Offset 07H (Read/Write).......................................................................... 34
5.1.3 Interrupt mask register (IMR) Offset 0FH (Write).................................................................................... 35
5.1.4 Data Configuration Register (DCR) Offset 0EH (Write).......................................................................... 35
5.1.5 Transmit Configuration Register (TCR) Offset 0DH (Write) .................................................................... 35
5.1.6 Transmit Status Register (TSR) Offset 04H (Read)................................................................................... 36
5.1.7 Receive Configuration (RCR) Offset 0CH (Write).................................................................................... 36
5.1.8 Receive Status Register (RSR) Offset 0CH (Read) ................................................................................... 36
5.1.9 Inter-frame gap (IFG) Offset 16H (Read/Write)....................................................................................... 37
5.1.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)................................................................. 37
5.1.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)................................................................. 37
5.1.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write)................................................. 37
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參數(shù)描述
AX88796ALF 制造商:ASIX 功能描述:10/100 MAC,COMMERCIAL 128PIN
AX88796BLF 制造商:Asix Electronics 功能描述:IEEE802.3 / IEEE802.3u LAN standard Ethernet 3.3V 64LQFP Tray 制造商:ASIX 功能描述:10/100 MAC,COMMERCIAL 64PIN
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AX88796C 制造商:ASIX 制造商全稱:ASIX 功能描述:Low-Power SPI or Non-PCI Ethernet Controller
AX88796CLF 制造商:ASIX Electronics Corporation 功能描述:
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