參數(shù)資料
型號(hào)： AX88796
廠商： Electronic Theatre Controls, Inc.
英文描述： 3-in-1 Local Bus Fast Ethernet Controller
中文描述： 3合1本地總線快速以太網(wǎng)控制器
文件頁(yè)數(shù)： 12/71頁(yè)
文件大?。?/td> 931K
代理商： AX88796
ASIX ELECTRONICS CORPORATION
12
AX88796 L 3-in-1 Local Bus Fast Ethernet Controller
2.0 Signal Description
The following terms describe the AX88796 pin-out:
All pin names with the “/” suffix are asserted low.
The following abbreviations are used in following Tables.
I
Input
O
Output
I/O
Input/Output
OD
Open Drain
2.1 Local CPU Bus Interface Signals Group
SIGNAL
TYPE
PIN NO.
SA[9:1],
SA[0]/LDS
12 – 4
PU
PD
P
Pull Up
Pull Down
Power Pin
DESCRIPTION
I
15,
System Address : Signals SA[9:0] are address bus input lines, which
lower I/O spaces on chip. SA[0] also means Lower Data Strobe
(/LDS) active low signal in 68K application mode.
Bus High Enable or Upper Data Strobe : Bus High Enable is active
low signal in some 16-bit application mode, which enable high bus
(SD[15:8]) active. The signal also name as Upper Data Strobe (/UDS)
for 68K application mode.
System Data Bus : Signals SD[15:0] constitute the bi-directional data
bus.
/BHE
or
/UDS
I/PU
22
SD[15:0]
I/O/PD
23 – 26,
29 – 33,
35 – 39,
41 – 42
16
IREQ/IREQ
O
Interrupt Request : When ISA BUS or 80186 CPU mode is select.
IREQ is asserted high to indicate the host system that the chip
requires host software service. When MC68K or MCS-51 CPU mode
is select. /IREQ is asserted low to indicate the host system that the
chip requires host software service.
Ready : This signal is set low to insert wait states during Remote
DMA transfer.
/Dtack : When Motorola CPU type is selected, the pin is active low
inform CPU that data is accepted.
Chip Select
When the /CS signal is asserted, the chip is selected.
I/O Read :The host asserts /IORD to read data from AX88796 I/O
space. When Motorola CPU type is select , the pin is useless.
I/O Write :The host asserts /IOWR to write data into AX88796 I/O
space. When Motorola CPU type is select, the pin is active high for
read operation at the same time.
I/O is 16 Bit Port : The /IOIS16 is asserted when the address at the
range corresponds to an I/O address to which the chip responds, and
the I/O port addressed is capable of 16-bit access.
Address Enable : The signal is asserted when the address bus is
available for DMA cycle. When negated (low), AX88796 an I/O slave
device may respond to addresses and I/O command.
PSEN : This signal is active low for 8051 program access. For I/O
device, AX88796, this signal is active high to access the chip. This
signal is for 8051 bus application only.
RDY/DTACK
OD
2
/CS
I/PU
128
/IORD
I/PU
19
/IOWR
or
R/W
/OCS16
I/PU
18
OD
123
AEN
or
/PSEN
I/PD
1
Tab - 1 Local CPU bus interface signals group
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參數(shù)描述
AX88796ALF 制造商:ASIX 功能描述:10/100 MAC,COMMERCIAL 128PIN
AX88796BLF 制造商:Asix Electronics 功能描述:IEEE802.3 / IEEE802.3u LAN standard Ethernet 3.3V 64LQFP Tray 制造商:ASIX 功能描述:10/100 MAC,COMMERCIAL 64PIN
AX88796BLI 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:High-Performance Non-PCI Single-Chip 8/16 bit 10/100M Fast Ethernet Controller
AX88796C 制造商:ASIX 制造商全稱(chēng):ASIX 功能描述:Low-Power SPI or Non-PCI Ethernet Controller
AX88796CLF 制造商:ASIX Electronics Corporation 功能描述:
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