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參數(shù)資料
| 型號(hào)： | AS4C4M4FOQ |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 5V 4M×4 CMOS QuadCAS DRAM （Fast Page Mode)(5V 4M×4 CMOS QuadCAS 動(dòng)態(tài)RAM（快速頁面模式）) |
| 中文描述： | 5V的4米× 4的CMOS QuadCAS的DRAM（快速頁面模式）（5V的4米× 4的CMOS QuadCAS動(dòng)態(tài)隨機(jī)存儲(chǔ)器（快速頁面模式）） |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 364K |
| 代理商： | AS4C4M4FOQ |
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The 4C4M4FOQ and AS4C4M4F1Q are high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) devices organized
as 4,194,304 words × 4 bits. The devices are fabricated using advanced CMOS technology and innovative design techniques resulting in high
speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for
use as main memory in PC, workstation, router and switch applications.
These devices feature a high speed page mode operation where read and write operations within a single row (or page) can be executed at
very high speed by toggling column addresses within tha row. Row and column addresses are alternately latched into input buffers using the
falling edge of RAS and CAS inputs respectively. Four individual CAS pins allow for separate I/O operation which enables the devices to
operate in parity mode. Also, RAS is used to make the column address latch transparent, enabling application of column addresses prior to
CAS assertion.
Refresh on the 4096 address combinations of A0 to A11 must be performed every 64 ms using:
RAS-only refresh: RAS is asserted while CAS is held high. Each of the 4096 rows must be strobed. Outputs remain high impedence.
Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
Normal read or write cycles refresh the row being accessed.
Self-refresh cycles
Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:
RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.
Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
Normal read or write cycles refresh the row being accessed.
Self-refresh cycles
The 4C4M4FOQ and AS4C4M4F1Q are available in the standard 28-pin plastic SOJ and 28-pin plastic TSOP packages. The 4C4M4FOQ and
AS4C4M4F1Q operate with a single power supply of 5V ± 0.5V and provide TTL compatible inputs and outputs.
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A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
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CC
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A
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Column decoder
Data
I/O
buffers
OE
RAS
CAS
WE clock
generator
WE
I/O0 to I/O3
CAS clock
generator
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