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參數(shù)資料
| 型號(hào)： | AM79C972BVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| 中文描述： | 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 65/130頁(yè) |
| 文件大小： | 1580K |
| 代理商： | AM79C972BVCW |
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Am79C972
65
are both operating at the same time so that the control-
ler receives its own transmissions. The controller pro-
vides two basic types of loopback. In internal loopback
mode, the transmitted data is looped back to the re-
ceiver inside the controller without actually transmitting
any data to the external network. The receiver will
move the received data to the next receive buffer,
where it can be examined by software. Alternatively, in
external loopback mode, data can be transmitted to
and received from the external network.
Refer to Table 21 for various bit settings required for
Loopback modes.
GPSI Loopback Modes
When GPSI is the active network port, there are only
two modes of loopback operation: internal and external
loopback. Loopback operation is enabled by setting
LOOP (CSR15, bit 2) to 1.
When INTL is set to 1, internal loopback is selected.
Data coming out of the transmit FIFO is fed directly to
the receive FIFO. All GPSI outputs are inactive; inputs
are ignored.
External loopback operation is selected by setting INTL
to 0. Data is transmitted to the network and is expected
to be looped back to the GPSI receive pins outside the
chip. Collision detection is active in this mode.
Media Independent Interface Loopback Features
Loopback through the MII can be handled in two ways.
The Am79C972 controller supports an internal MII
loopback and an external MII loopback. The MII
loopback requires that the MII port be manually config-
ured through software using ASEL (BCR 2, bit 1) and
PORTSEL (CSR 15, bits 8-7).
The external loopback through the MII requires a two-
step operation. The external PHY must be placed into
a loopback mode by writing to the MII Control Register
(BCR33, BCR34). Then the Am79C972 controller must
be placed into an external loopback mode by setting
the Loop bits.
The internal loopback through the MII is controlled by
MIIILP (BCR32, bit 1). When set to 1, this bit will cause
the internal portion of the MII data port to loopback on
itself. The MII management port (MDC, MDIO) is unaf-
fected by the MIILP bit. The internal MII interface is
mapped in the following way:
The TXD[3:0] nibble data path is looped back onto
the RXD[3:0] nibble data path;
TX_CLK is looped back as RX_CLK;
TX_EN is looped back as RX_DV.
CRS is correctly OR
’
d with TX_EN and RX_DV and
always encompasses the transmit frame.
TX_ER is not driven by the Am79C972 and there-
fore not looped back.
During the internal loopback, the TXD, TX_CLK, and
TX_EN pins will toggle appropriately with the correct
data.
Miscellaneous Loopback Features
All transmit and receive function programming, such as
automatic transmit padding and receive pad stripping,
operates identically in loopback as in normal operation.
Runt Packet Accept is internally enabled (RPA bit in
CSR124 is not affected) when any loopback mode is in-
voked. This is to be backwards compatible to the C-
LANCE (Am79C90) software.
Since the Am79C972 controller has two FCS genera-
tors, there are no more restrictions on FCS generation
or checking, or on testing multicast address detection
as they exist in the half-duplex PCnet family devices
and in the C-LANCE. On receive, the Am79C972 con-
troller now provides true FCS status. The descriptor for
a frame with an FCS error will have the FCS bit (RMD1,
bit 27) set to 1. The FCS generator on the transmit side
can still be disabled by setting DXMTFCS (CSR15, bit
3) to 1.
In internal loopback operation, the Am79C972 control-
ler provides a special mode to test the collision logic.
When FCOLL (CSR15, bit 4) is set to 1, a collision is
forced during every transmission attempt. This will re-
sult in a Retry error.
General Purpose Serial Interface
The General Purpose Serial Interface (GPSI) provides
a direct interface to the MAC section of the Am79C972
controller. All signals are digital and data is non-en-
coded. The GPSI allows use of an external Manchester
encoder/decoder such as the Am7992B Serial Inter-
face Adapter (SIA). In addition, it allows the Am79C972
controller to be used as a MAC sublayer engine in re-
peater designs based on the IMR+ device
(Am79C981).
GPSI mode is invoked by selecting the interface
through the PORTSEL bits of the Mode register
(CSR15, bits 8-7).
The GPSI interface uses some of the same pins as the
interface to the MII. Simultaneous use of both functions
is not possible.
After an H_RESET, all MII pins are internally config-
ured to function as the MII interface. When the GPSI in-
terface is selected by setting PORTSEL (CSR15, bits
8-7) to 10b, the Am79C972 controller will terminate all
further accesses to the MII.
GPSI signal functions are described in the pin descrip-
tion section under the GPSI subheading.
Full-Duplex Operation
The Am79C972 controller supports full-duplex opera-
tion on both network interfaces. Full-duplex operation
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