參數(shù)資料
型號(hào)： AM79C972BVCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
中文描述： 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176
封裝： TQFP-176
文件頁(yè)數(shù)： 117/130頁(yè)
文件大?。?/td> 1580K
代理商： AM79C972BVCW
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Am79C972
117
ed by S_RESET or by setting the
STOP bit.
13
RDMD
Receive Demand, when set,
causes the Buffer Management
Unit to access the Receive De-
scriptor Ring without waiting for
the receive poll-time counter to
elapse. If RXON is not enabled,
RDMD has no meaning and no
receive Descriptor Ring access
will occur.
RDMD is required to be set if the
RXDPOLL bit in CSR7 is set. Set-
ting RDMD while RXDPOLL = 0
merely hastens the Am79C972
controller
’
s response to a receive
Descriptor Ring Entry.
Read/Write accessible always.
RDMD is set by writing a 1. Writ-
ing a 0 has no effect. RDMD will
be cleared by the Buffer Manage-
ment Unit when it fetches a re-
ceive
Descriptor.
cleared by H_RESET. RDMD is
unaffected by S_RESET or by
setting the STOP bit.
RDMD
is
12
RXDPOLL
Receive Disable Polling. If RXD-
POLL is set, the Buffer Manage-
ment Unit will disable receive
polling. Likewise, if RXDPOLL is
cleared, automatic receive poll-
ing is enabled. If RXDPOLL is
set, RDMD bit in CSR7 must be
set in order to initiate a manual
poll of a receive descriptor. Re-
ceive Descriptor Polling will not
take place if RXON is reset.
Read/Write accessible always.
RXDPOLL
is
H_RESET. RXDPOLL is unaf-
fected by S_RESET or by setting
the STOP bit.
cleared
by
11
STINT
Software Timer Interrupt. The
Software Timer interrupt is set by
the Am79C972 controller when
the Software Timer counts down
to 0. The Software Timer will im-
mediately load the STVAL (BCR
31, bits 5-0) into the Software
Timer and begin counting down.
When STINT is set to 1, INTA is
asserted if the enable bit STINTE
is set to 1.
Read/Write accessible always.
STINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
STINT
is
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
cleared
by
10
STINTE
Software Timer Interrupt Enable.
If STINTE is set, the STINT bit
will be able to set the INTR bit.
Read/Write accessible always.
STINTE is set to 0 by H_RESET
and is not affected by S_RESET
or setting the STOP bit
9
MREINT
MII Management Read Error In-
terrupt. The MII Read Error inter-
rupt is set by the Am79C972
controller to indicate that the cur-
rently read register from the ex-
ternal PHY is invalid. The
contents of BCR34 are incorrect
and that the operation should be
performed again. The indication
of an incorrect read comes from
the PHY. During the read turn-
around time of the MII manage-
ment frame the external PHY
should drive the MDIO pin to a
LOW state. If this does not hap-
pen, it indicates that the PHY and
the Am79C972 controller have
lost synchronization.
When MREINT is set to 1, INTA is
asserted if the enable bit MREIN-
TE is set to 1.
Read/Write accessible always.
MREINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect. MREINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
8
MREINTE
MII Management Read Error In-
terrupt Enable. If MREINTE is
set, the MREINT bit will be able to
set the INTR bit.
Read/Write accessible always.
MREINTE is set to 0 by
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