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參數資料
| 型號： | AM79C972BVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| 中文描述： | 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁數： | 32/130頁 |
| 文件大?。?/td> | 1580K |
| 代理商： | AM79C972BVCW |
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32
Am79C972
If the host is not yet ready when the Am79C972 control-
ler asserts TRDY, the device will wait for the host to as-
sert IRDY. When the host asserts IRDY and FRAME is
still asserted, the Am79C972 controller will finish the
first data phase by deasserting TRDY one clock later.
At the same time, it will assert STOP to signal a discon-
nect to the host. STOP will stay asserted until the host
removes FRAME. See Figure 8.
Figure 8.
Disconnect Of Slave Burst Transfer -
Host Inserts Wait States
Parity Error Response
When the Am79C972 controller is not the current bus
master, it samples the AD[31:0], C/BE[3:0], and the
PAR lines during the address phase of any PCI com-
mand for a parity error. When it detects an address par-
ity error, the controller sets PERR (PCI Status register,
bit 15) to 1. When reporting of that error is enabled by
setting SERREN (PCI Command register, bit 8) and
PERREN (PCI Command register, bit 6) to 1, the
Am79C972 controller also drives the SERR signal low
for one clock cycle and sets SERR (PCI Status register,
bit 14) to 1. The assertion of SERR follows the address
phase by two clock cycles. The Am79C972 controller
will not assert DEVSEL for a PCI transaction that has
an address parity error when PERREN and SERREN
are set to 1. See Figure 9.
Figure 9.
Address Parity Error Response
During the data phase of an I/O write, memory-mapped
I/O write, or configuration write command that selects
the Am79C972 controller as target, the device samples
the AD[31:0] and C/BE[3:0] lines for parity on the clock
edge, and data is transferred as indicated by the asser-
tion of IRDY and TRDY. PAR is sampled in the following
clock cycle. If a parity error is detected and reporting of
that error is enabled by setting PERREN (PCI Com-
mand register, bit 6) to 1, PERR is asserted one clock
later. The parity error will always set PERR (PCI Status
register, bit 15) to 1 even when PERREN is cleared to
0. The Am79C972 controller will finish a transaction
that has a data parity error in the normal way by assert-
ing TRDY. The corrupted data will be written to the ad-
dressed location.
Figure 10 shows a transaction that suffered a parity
error at the time data was transferred (clock 7, IRDY
and TRDY are both asserted). PERR is driven high at
the beginning of the data phase and then drops low due
to the parity error on clock 9, two clock cycles after the
data was transferred. After PERR is driven low, the
Am79C972 controller drives PERR high for one clock
cycle, since PERR is a sustained tri-state signal.
FRAME
CLK
AD
IRDY
TRDY
C/BE
DEVSEL
STOP
1
2
3
4
5
6
PAR
BE
PAR
PAR
BE
DATA
1st DATA
21485C-11
FRAME
CLK
AD
SERR
C/BE
DEVSEL
1
2
3
4
5
PAR
PAR
ADDR
1st DATA
BE
CMD
PAR
21485C-12
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相關代理商/技術參數 |
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