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參數(shù)資料
| 型號(hào)： | AM79C972BVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| 中文描述： | 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 58/130頁(yè) |
| 文件大?。?/td> | 1580K |
| 代理商： | AM79C972BVCW |
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58
Am79C972
gine provides facilities for physical (unicast), logical
(multicast), and broadcast address reception.
Error Detection
The MAC engine provides several facilities which re-
port and recover from errors on the medium. In addi-
tion, it protects the network from gross errors due to
inability of the host to keep pace with the MAC engine
activity.
On completion of transmission, the following transmit
status is available in the appropriate Transmit Message
Descriptor (TMD) and Control and Status Register
(CSR) areas:
The number of transmission retry attempts (ONE,
MORE, RTRY, and TRC).
Whether the MAC engine had to Defer (DEF) due to
channel activity.
Excessive deferral (EXDEF), indicating that the
transmitter experienced Excessive Deferral on this
transmit frame, where Excessive Deferral is defined
in the ISO 8802-3 (IEEE/ANSI 802.3) standard.
Loss of Carrier (LCAR), indicating that there was an
interruption in the ability of the MAC engine to mon-
itor its own transmission. Repeated LCAR errors in-
dicate a potentially faulty transceiver or network
connection.
Late Collision (LCOL) indicates that the transmis-
sion suffered a collision after the slot time. This is in-
dicative of a badly configured network. Late
collisions should not occur in a normal operating
network.
Collision Error (CERR) indicates that the trans-
ceiver did not respond with an SQE Test message
within the first 4
μ
s after a transmission was com-
pleted. This may be due to a failed transceiver, dis-
connected or faulty transceiver drop cable, or
because the transceiver does not support this fea-
ture (or it is disabled). SQE Test is only valid for 10-
Mbps networks.
In addition to the reporting of network errors, the MAC
engine will also attempt to prevent the creation of any
network error due to the inability of the host to service
the MAC engine. During transmission, if the host fails
to keep the transmit FIFO filled sufficiently, causing an
underflow, the MAC engine will guarantee the message
is either sent as a runt packet (which will be deleted by
the receiving station) or as an invalid FCS (which will
also cause the receiver to reject the message).
The status of each receive message is available in the
appropriate Receive Message Descriptor (RMD) and
CSR areas. All received frames are passed to the host
regardless of any error. The FRAM error will only be re-
ported if an FCS error is detected and there is a non-
integral number of bytes in the message.
During the reception, the FCS is generated on every
nibble (including the dribbling bits) coming from the ca-
ble, although the internally saved FCS value is only up-
dated on the eighth bit (on each byte boundary). The
MAC engine will ignore up to 7 additional bits at the end
of a message (dribbling bits), which can occur under
normal network operating conditions. The framing error
is reported to the user as follows:
If the number of dribbling bits are 1 to 7 and there is
no FCS error, then there is no Framing error (FRAM
= 0).
If the number of dribbling bits are 1 to 7 and there is
a FCS error, then there is also a Framing error
(FRAM = 1).
If the number of dribbling bits is 0, then there is no
Framing error. There may or may not be a FCS er-
ror.
If the number of dribbling bits is EIGHT, then there
is no Framing error. FCS error will be reported and
the receive message count will indicate one extra
byte.
Media Access Management
The basic requirement for all stations on the network is
to provide fairness of channel allocation. The IEEE
802.3/Ethernet protocols define a media access mech-
anism which permits all stations to access the channel
with equality. Any node can attempt to contend for the
channel by waiting for a predetermined time (Inter
Packet Gap) after the last activity, before transmitting
on the media. The channel is a multidrop communica-
tions media (with various topological configurations
permitted), which allows a single station to transmit and
all other stations to receive. If two nodes simulta-
neously contend for the channel, their signals will inter-
act causing loss of data, defined as a collision. It is the
responsibility of the MAC to attempt to avoid and
recover from a collision, to guarantee data integrity for
the end-to-end transmission to the receiving station.
Medium Allocation
The IEEE/ANSI 802.3 standard (ISO/IEC 8802-3 1990)
requires that the CSMA/CD MAC monitor the medium
for traffic by watching for carrier activity. When carrier is
detected, the media is considered busy, and the MAC
should defer to the existing message.
The ISO 8802-3 (IEEE/ANSI 802.3) standard also al-
lows optionally a two-part deferral after a receive mes-
sage.
See ANSI/IEEE Std 802.3-1993 Edition, 4.2.3.2.1:
Note:
It is possible for the PLS carrier sense indication
to fail to be asserted during a collision on the media. If
the deference process simply times the inter-Frame
gap based on this indication, it is possible for a short in-
terFrame gap to be generated, leading to a potential
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AM79C972BVD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C972BVD\W | 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 176-Pin TQFP Tray |
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| AM79C973 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973/75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Board Layout Considerations for the Am79C973/75 Network Interface? - (PDF) |
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