參數(shù)資料
型號: AM79C972BVIW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
中文描述: 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176
封裝: TQFP-176
文件頁數(shù): 1/130頁
文件大?。?/td> 1580K
代理商: AM79C972BVIW
Publication#
21485
Issue Date:
December 1999
Rev:
D
Amendment/
0
Refer to AMD’s Website (www.amd.com) for the latest information.
Am79C972
PCnet-
FAST+
Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
DISTINCTIVE CHARACTERISTICS
Integrated Fast Ethernet controller for the
Peripheral Component Interconnect (PCI) bus
32-bit glueless PCI host interface
Supports PCI clock frequency from DC to
33 MHz independent of network clock
Supports network operation with PCI clock
from 15 MHz to 33 MHz
High performance bus mastering
architecture with integrated Direct Memory
Access (DMA) Buffer Management Unit for
low CPU and bus utilization
PCI specification revision 2.1 compliant
Supports PCI Subsystem/Subvendor ID/
Vendor ID programming through the
EEPROM interface
Supports both PCI 3.3-V and 5.0-V signaling
environments
Plug and Play compatible
Supports an unlimited PCI burst length
Big endian and little endian byte alignments
supported
Implements optional PCI power management
event (PME) pin
Media Independent Interface (MII) for
connecting external 10/100 megabit per second
(Mbps) transceivers
IEEE 802.3-compliant MII
Intelligent Auto-Poll
external PHY status
monitor and interrupt
Supports both auto-negotiable and non
auto-negotiable external PHYs
Supports 10BASE-T, 100BASE-TX/FX,
100BASE-T4, and 100BASE-T2 IEEE 802.3-
compliant MII PHYs at full- or half-duplex
Supports General Purpose Serial Interface
(GPSI) with receive frame tagging support for
internetworking applications
Full-duplex operation supported in MII and GPSI
ports with independent Transmit (TX) and
Receive (RX) channels
Supports PC97, PC98, and Net PC requirements
Implements full OnNow features including
pattern matching and link status wake-up
Implements Magic Packet mode
Magic Packet mode and the physical address
loaded from EEPROM at power up without
requiring PCI clock
Supports PCI Bus Power Management
Interface Specification Version 1.0
Supports Advanced Configuration and
Power Interface (ACPI) Specification
Version 1.0
Supports Network Device Class Power
Management Specification Version 1.0
Large independent internal TX and RX FIFOs
Programmable FIFO watermarks for both
transmit and receive operations
Receive frame queuing for high latency PCI
bus host operation
Programmable allocation of buffer space
between transmit and receive queues
Dual-speed CSMA/CD (10 Mbps and 100 Mbps)
Media Access Controller (MAC) compliant with
IEEE/ANSI 802.3 and Blue Book Ethernet
standards
EEPROM interface supports jumperless design
and provides through-chip programming
Supports full programmability of half-/full-
duplex operation for external 10/100 Mbps
PHYs through EEPROM mapping
Programmable PHY reset output pin capable
of resetting external PHY without needing
buffering
Integrated oscillator circuit eliminates need for
external crystal
Extensive programmable LED status support
Support for operation in industrial temperature
range (-40
°
C to +85
°
C)
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