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參數(shù)資料
| 型號： | AM79C972BVIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| 中文描述： | 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁數(shù)： | 66/130頁 |
| 文件大?。?/td> | 1580K |
| 代理商： | AM79C972BVIW |
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66
Am79C972
allows simultaneous transmit and receive activity on the
TXDAT and RXDAT pins of the GPSI port, and the
TXD[3:0] and RXD[3:0] pins of the MII port. Full-duplex
operation is enabled by the FDEN bit located in BCR9
for all ports. Full-duplex operation is also enabled
through Auto-Negotiation when DANAS (BCR 32, bit 7)
is not enabled on the MII port and the ASEL bit is set,
and both the external PHY and its link partner are ca-
pable of Auto-Negotiation and full-duplex operation.
When operating in full-duplex mode, the following
changes to the device operation are made:
Bus Interface/Buffer Management Unit changes:
The first 64 bytes of every transmit frame are not
preserved in the Transmit FIFO during transmission
of the first 512 bits as described in the Transmit Ex-
ception Conditions section. Instead, when full-du-
plex mode is active and a frame is being transmitted,
the XMTFW bits (CSR80, bits 9-8) always
govern
when transmit DMA is requested.
Successful reception of the first 64 bytes of every
receive frame is not a requirement for Receive DMA
to begin as described in the Receive Exception Con-
ditions section. Instead, receive DMA will be re-
quested as soon as either the RCVFW threshold
(CSR80, bits 12-13) is reached or a complete valid
receive frame is detected, regardless of length. This
Receive FIFO operation is identical to when the RPA
bit (CSR124, bit 3) is set during half-duplex mode
operation.
The MAC engine changes for full-duplex operation are
as follows:
Changes to the Transmit Deferral mechanism:
—
Transmission is not deferred while receive is
active.
—
The IPG counter which governs transmit deferral
during the IPG between back-to-back transmits
is started when transmit activity for the first
packet ends, instead of when transmit and car-
rier activity ends.
The 4.0 μs carrier sense blinding period after a
transmission during which the SQE test normally
occurs is disabled.
The collision indication input to the MAC engine is
ignored.
The MII changes for full-duplex operation are as fol-
lows:
The collision detect (COL) pin is disabled.
The SQE test function is disabled.
Loss of Carrier (LCAR) reporting is disabled.
Full-Duplex Link Status LED Support
The Am79C972 controller provides bits in each of the
LED Status registers (BCR4, BCR5, BCR6, BCR7) to
display the Full-Duplex Link Status. If the FDLSE bit (bit
8) is set, a value of 1 will be sent to the associated LED-
OUT bit when in Full-Duplex.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C973 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973/75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Board Layout Considerations for the Am79C973/75 Network Interface? - (PDF) |
| AM79C973/AM79C975 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am79C973/Am79C975 - PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973AVC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C973AVC\W | 制造商:Advanced Micro Devices 功能描述: |
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