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50
Am79C972
Figure 30.
FIFO Burst Write At End Of Unaligned
Buffer
The exact number of total transfer cycles in the bus
mastership period is dependent on all of the following
variables: the settings of the FIFO watermarks, the
conditions of the FIFOs, the latency of the system bus
to the Am79C972 controller
’
s bus request, and the
speed of bus operation. The TRDY response time of
the memory device will also affect the number of trans-
fers, since the speed of the accesses will affect the
state of the FIFO. During accesses, the FIFO may be
filling or emptying on the network end. For example, on
a receive operation, a slower TRDY response will allow
additional data to accumulate inside of the FIFO. If the
accesses are slow enough, a complete DWord may be-
come available before the end of the bus mastership
period and, thereby, increase the number of transfers in
that period. The general rule is that the longer the Bus
Grant latency, the slower the bus transfer operations;
the slower the clock speed, the higher the transmit wa-
termark; or the lower the receive watermark, the longer
the total burst length will be.
When a FIFO DMA burst operation is preempted, the
Am79C972 controller will not relinquish bus ownership
until the PCI Latency Timer expires.
Buffer Management Unit
The Buffer Management Unit (BMU) is a microcoded
state machine which implements the initialization pro-
cedure and manages the descriptors and buffers. The
buffer management unit operates at half the speed of
the CLK input.
Initialization
Am79C972 initialization includes the reading of the ini-
tialization block in memory to obtain the operating pa-
rameters. The initialization block can be organized in
two ways. When SSIZE32 (BCR20, bit 8) is at its de-
fault value of 0, all initialization block entries are logi-
cally 16-bits wide to be backwards compatible with the
Am79C90 C-LANCE and Am79C96x PCnet-ISA family.
When SSIZE32 (BCR20, bit 8) is set to 1, all initializa-
tion block entries are logically 32-bits wide. Note that
the Am79C972 controller always performs 32-bit bus
transfers to read the initialization block entries. The ini-
tialization block is read when the INIT bit in CSR0 is set.
The INIT bit should be set before or concurrent with the
STRT bit to insure correct operation. Once the initial-
ization block has been completely read in and internal
registers have been updated, IDON will be set in
CSR0, generating an interrupt (if IENA is set).
The Am79C972 controller obtains the start address of
the initialization block from the contents of CSR1 (least
significant 16 bits of address) and CSR2 (most signifi-
cant 16 bits of address). The host must write CSR1 and
CSR2 before setting the INIT bit. The initialization block
contains the user defined conditions for Am79C972 op-
eration, together with the base addresses and length
information of the transmit and receive descriptor rings.
There is an alternate method to initialize the
Am79C972 controller. Instead of initialization via the
initialization block in memory, data can be written di-
rectly into the appropriate registers. Either method or a
combination of the two may be used at the discretion of
the programmer. Please refer to
Appendix A, Alterna-
tive Method for Initialization
for details on this alternate
method.
Re-Initialization
The transmitter and receiver sections of the Am79C972
controller can be turned on via the initialization block
(DTX, DRX, CSR15, bits 1-0). The states of the trans-
mitter and receiver are monitored by the host through
CSR0 (RXON, TXON bits). The Am79C972 controller
should be re-initialized if the transmitter and/or the re-
ceiver were not turned on during the original initializa-
tion, and it was subsequently required to activate them
or if either section was shut off due to the detection of
an error condition (MERR, UFLO, TX BUFF error).
Re-initialization may be done via the initialization block
or by setting the STOP bit in CSR0, followed by writing
FRAME
CLK
AD
IRDY
TRDY
C/BE
DEVSEL
REQ
GNT
1
2
3
4
5
6
7
0000
0111
PAR
PAR
PAR
PAR
DEVSEL is sampled
1110
PAR
DATA
DATA
DATA
ADD
21485C-33
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| AM79C974 | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AM79C973 | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973/75 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Board Layout Considerations for the Am79C973/75 Network Interface? - (PDF) |
| AM79C973/AM79C975 | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Am79C973/Am79C975 - PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973AVC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C973AVC\W | 制造商:Advanced Micro Devices 功能描述: |
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