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參數(shù)資料
| 型號(hào)： | AM79C972BVIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| 中文描述： | 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 59/130頁(yè) |
| 文件大?。?/td> | 1580K |
| 代理商： | AM79C972BVIW |
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Am79C972
59
reception failure of a subsequent frame. To enhance
system robustness, the following optional measures,
as specified in 4.2.8, are recommended when Inter-
Frame-SpacingPart1 is other than 0:
1. Upon completing a transmission, start timing the in-
terrupted gap, as soon as transmitting and carrier
sense are both false.
2. When timing an inter-frame gap following reception,
reset the inter-frame gap timing if carrier sense be-
comes true during the first 2/3 of the inter-frame gap
timing interval. During the final 1/3 of the interval,
the timer shall not be reset to ensure fair access to
the medium. An initial period shorter than 2/3 of the
interval is permissible including 0.
The MAC engine implements the optional receive two
part deferral algorithm, with an InterFrameSpacing-
Part1 time of 6.0
μ
s. The InterFrameSpacingPart 2 in-
terval is, therefore, 3.4
μ
s.
The Am79C972 controller will perform the two-part
deferral algorithm as specified in Section 4.2.8 (Pro-
cess Deference). The Inter Packet Gap (IPG) timer will
start timing the 9.6
μ
s InterFrameSpacing after the re-
ceive carrier is deasserted. During the first part deferral
(InterFrameSpacingPart1 - IFS1), the Am79C972 con-
troller will defer any pending transmit frame and re-
spond to the receive message. The IPG counter will be
cleared to 0 continuously until the carrier deasserts, at
which point the IPG counter will resume the 9.6
μ
s
count once again. Once the IFS1 period of 6.0
μ
s has
elapsed, the Am79C972 controller will begin timing the
second part deferral (InterFrameSpacingPart2 - IFS2)
of 3.4
μ
s. Once IFS1 has completed and IFS2 has com-
menced, the Am79C972 controller will not defer to a re-
ceive frame if a transmit frame is pending. This means
that the Am79C972 controller will not attempt to receive
the receive frame, since it will start to transmit and gen-
erate a collision at 9.6
μ
s. The Am79C972 controller
will complete the preamble (64-bit) and jam (32-bit) se-
quence before ceasing transmission and invoking the
random backoff algorithm.
The Am79C972 controller allows the user to program
the IPG and the first part deferral (InterFrame-
SpacingPart1 - IFS1) through CSR125. By changing
the IPG default value of 96 bit times (60h), the user can
adjust the fairness or aggressiveness of the
Am79C972 MAC on the network. By programming a
lower number of bit times than the ISO/IEC 8802-3
standard requires, the Am79C972 MAC engine will be-
come more aggressive on the network. This aggressive
nature will give rise to the Am79C972 controller possi-
bly
capturing the network
at times by forcing other less
aggressive compliant nodes to defer. By programming
a larger number of bit times, the Am79C972 MAC will
become less aggressive on the network and may defer
more often than normal. The performance of the
Am79C972 controller may decrease as the IPG value
is increased from the default value, but the resulting be-
havior may improve network performance by reducing
collisions. The Am79C972 controller uses the same
IPG for back-to-back transmits and receive-to-transmit
accesses. Changing IFS1 will alter the period for which
the Am79C972 MAC engine will defer to incoming re-
ceive frames.
CAUTION: Care must be exercised when altering
these parameters
.
Adverse network activity could
result!
This transmit two-part deferral algorithm is imple-
mented as an option which can be disabled using the
DXMT2PD bit in CSR3. The IFS1 programming will
have no effect when DXMT2PD is set to 1, but the IPG
programming value is still valid. Two part deferral after
transmission is useful for ensuring that severe IPG
shrinkage cannot occur in specific circumstances,
causing a transmit message to follow a receive mes-
sage so closely as to make them indistinguishable.
During the time period immediately after a transmission
has been completed, the external transceiver should
generate the SQE Test message within 0.6 to 1.6
μ
s
after the transmission ceases. During the time period in
which the SQE Test message is expected, the
Am79C972 controller will not respond to receive carrier
sense.
See ANSI/IEEE Std 802.3-1993 Edition, 7.2.4.6 (1):
“
At the conclusion of the output function, the DTE
opens a time window during which it expects to see
the signal_quality_error signal asserted on the
Control In circuit. The time window begins when
the
CARRIER_STATUS
CARRIER_OFF. If execution of the output function
does not cause CARRIER_ON to occur, no SQE
test occurs in the DTE. The duration of the window
shall be at least 4.0
μ
s but no more than 8.0
μ
s.
During the time window the Carrier Sense Function
is inhibited.
”
becomes
The Am79C972 controller implements a carrier sense
“
blinding
”
period of 4.0
μ
s length starting from the
deassertion of carrier sense after transmission. This ef-
fectively means that when transmit two part deferral is
enabled (DXMT2PD is cleared), the IFS1 time is from
4
μ
s to 6
μ
s after a transmission. However, since IPG
shrinkage below 4
μ
s will rarely be encountered on a
correctly configured network, and since the fragment
size will be larger than the 4
μ
s blinding window, the
IPG counter will be reset by a worst case IPG shrink-
age/fragment scenario and the Am79C972 controller
will defer its transmission. If carrier is detected within
the 4.0 to 6.0
μ
s IFS1 period, the Am79C972 controller
will not restart the
“
blinding
”
period, but only restart
IFS1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C974 | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| AM79C974KCW | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| AM79C975 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C973 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973/75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Board Layout Considerations for the Am79C973/75 Network Interface? - (PDF) |
| AM79C973/AM79C975 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am79C973/Am79C975 - PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973AVC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C973AVC\W | 制造商:Advanced Micro Devices 功能描述: |
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