參數(shù)資料
型號: AM79C972BVCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
中文描述: 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176
封裝: TQFP-176
文件頁數(shù): 33/130頁
文件大小: 1580K
代理商: AM79C972BVCW
Am79C972
33
Figure 10.
Slave Cycle Data Parity Error Response
Master Bus Interface Unit
The master Bus Interface Unit (BIU) controls the acqui-
sition of the PCI bus and all accesses to the initializa-
tion block, descriptor rings, and the receive and
transmit buffer memory. Table 3 shows the usage of
PCI commands by the Am79C972 controller in master
mode.
Bus Acquisition
The Am79C972 microcode will determine when a DMA
transfer should be initiated. The first step in any
Am79C972 bus master transfer is to acquire ownership
of the bus. This task is handled by synchronous logic
within the BIU. Bus ownership is requested with the
REQ signal and ownership is granted by the arbiter
through the GNT signal.
FRAME
CLK
AD
IRDY
TRDY
C/BE
DEVSEL
PAR
ADDR
CMD
PAR
1
2
3
4
5
6
7
8
10
9
DATA
PAR
BE
PERR
21485C-13
Table 3.
Master Commands
C[3:0]
Command
Interrupt
Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Use
0000
Not used
0001
0010
0011
0100
0101
Not used
Not used
Not used
0110
Memory Read
Read of the initialization
block and descriptor
rings
Read of the transmit
buffer in non-burst mode
0111
Memory Write
Write to the descriptor
rings and to the re-
ceive buffer
1000
C[3:0]
1001
1010
1011
Reserved
Command
Reserved
Configuration Read
Configuration Write
Memory Read
Multiple
Dual Address Cycle Not used
Use
Not used
Not used
Read of the transmit
buffer in burst mode
1100
1101
1110
Memory Read Line
Read of the transmit
buffer in burst mode
1111
Memory Write
Invalidate
Not used
Table 3.
Master Commands (Continued)
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