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參數(shù)資料
| 型號(hào)： | AM79C972BVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| 中文描述： | 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 34/130頁(yè) |
| 文件大小： | 1580K |
| 代理商： | AM79C972BVCW |
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34
Am79C972
Figure 11 shows the Am79C972 controller bus acquisi-
tion. REQ is asserted and the arbiter returns GNT while
another bus master is transferring data. The
Am79C972 controller waits until the bus is idle (FRAME
and IRDY deasserted) before it starts driving AD[31:0]
and C/BE[3:0] on clock 5. FRAME is asserted at clock
5 indicating a valid address and command on AD[31:0]
and C/BE[3:0]. The Am79C972 controller does not use
address stepping which is reflected by ADSTEP (bit 7)
in the PCI Command register being hardwired to 0.
Figure 11.
Bus Acquisition
In burst mode, the deassertion of REQ depends on the
setting of EXTREQ (BCR18, bit 8). If EXTREQ is
cleared to 0, REQ is deasserted at the same time as
FRAME is asserted. (The Am79C972 controller never
performs more than one burst transaction within a sin-
gle bus mastership period.) If EXTREQ is set to 1, the
Am79C972 controller does not deassert REQ until it
starts the last data phase of the transaction.
Once asserted, REQ remains active until GNT has be-
come active and independent of subsequent setting of
STOP (CSR0, bit 2) or SPND (CSR5, bit 0). The asser-
tion of H_RESET or S_RESET, however, will cause
REQ to go inactive immediately.
Bus Master DMA Transfers
There are four primary types of DMA transfers. The
Am79C972 controller uses non-burst as well as burst
cycles for read and write access to the main memory.
Basic Non-Burst Read Transfer
By default, the Am79C972 controller uses non-burst
cycles in all bus master read operations. All Am79C972
controller non-burst read accesses are of the PCI
command type Memory Read (type 6). Note that during
a non-burst read operation, all byte lanes will always be
active. The Am79C972 controller will internally discard
unneeded bytes.
The Am79C972 controller typically performs more than
one non-burst read transaction within a single bus mas-
tership period. FRAME is dropped between consecu-
tive non-burst read cycles. REQ however stays
asserted until FRAME is asserted for the last transac-
tion. The Am79C972 controller supports zero wait state
read cycles. It asserts IRDY immediately after the ad-
dress phase and at the same time starts sampling
DEVSEL. Figure 12 shows two non-burst read transac-
tions. The first transaction has zero wait states. In the
second transaction, the target extends the cycle by as-
serting TRDY one clock later.
Basic Burst Read Transfer
The Am79C972 controller supports burst mode for all
bus master read operations. The burst mode must be
enabled by setting BREADE (BCR18, bit 6). To allow
burst transfers in descriptor read operations, the
Am79C972 controller must also be programmed to use
SWSTYLE 3 (BCR20, bits 7-0). All burst read accesses
to the initialization block and descriptor ring are of the
PCI command type Memory Read (type 6). Burst read
accesses to the transmit buffer typically are longer than
two data phases. When MEMCMD (BCR18, bit 9) is
cleared to 0, all burst read accesses to the transmit
buffer are of the PCI command type Memory Read Line
(type 14). When MEMCMD (BCR18, bit 9) is set to1, all
burst read accesses to the transmit buffer are of the
PCI command type Memory Read Multiple (type 12).
AD[1:0] will both be 0 during the address phase indicat-
ing a linear burst order. Note that during a burst read
operation, all byte lanes will always be active. The
Am79C972 controller will internally discard unneeded
bytes.
The Am79C972 controller will always perform only a
single burst read transaction per bus mastership pe-
riod, where
transaction
is defined as one address
phase and one or multiple data phases. The
Am79C972 controller supports zero wait state read cy-
cles. It asserts IRDY immediately after the address
phase and at the same time starts sampling DEVSEL.
FRAME is deasserted when the next to last data phase
is completed.
Figure 13 shows a typical burst read access. The
Am79C972 controller arbitrates for the bus, is granted
access, reads three 32-bit words (DWord) from the sys-
tem memory, and then releases the bus. In the exam-
ple, the memory system extends the data phase of
each access by one wait state. The example assumes
that EXTREQ (BCR18, bit 8) is cleared to 0, therefore,
REQ is deasserted in the same cycle as FRAME is as-
serted.
FRAME
CLK
AD
IRDY
C/BE
REQ
GNT
1
2
3
4
5
CMD
ADDR
21485C-14
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C972BVD\\W | 制造商:Advanced Micro Devices 功能描述: |
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| AM79C972BVIW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C973 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973/75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Board Layout Considerations for the Am79C973/75 Network Interface? - (PDF) |
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