參數(shù)資料
型號： AM79C972BVCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
中文描述： 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176
封裝： TQFP-176
文件頁數(shù)： 110/130頁
文件大?。?/td> 1580K
代理商： AM79C972BVCW
110
Am79C972
or S_RESET and is not affected
by STOP.
9
TINTM
Transmit
TINTM is set, the TINT bit will be
masked and unable to set the
INTR bit.
Interrupt
Mask.
If
Read/Write accessible always.
TINTM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
8
IDONM
Initialization
IDONM is set, the IDON bit will be
masked and unable to set the
INTR bit.
Done
Mask.
If
Read/Write accessible always.
IDONM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
7
RES
Reserved location. Read and
written as zeros.
6
DXSUFLO
Disable Transmit Stop on Under-
flow error.
When DXSUFLO (CSR3, bit 6) is
set to 0, the transmitter is turned
off when an UFLO error occurs
(CSR0, TXON = 0).
When DXSUFLO is set to 1, the
Am79C972 controller gracefully
recovers from an UFLO error. It
scans the transmit descriptor ring
until it finds the start of a new
frame and starts a new transmis-
sion.
Read/Write accessible always.
DXSUFLO
is
H_RESET or S_RESET and is
not affected by STOP.
cleared
by
5
LAPPEN
Look Ahead Packet Processing
Enable. When set to a 1, the
LAPPEN bit will cause the
Am79C972 controller to generate
an interrupt following the descrip-
tor write operation to the first buff-
er of a receive frame. This
interrupt will be generated in ad-
dition to the interrupt that is gen-
erated following the descriptor
write operation to the last buffer
of a receive packet. The interrupt
will be signaled through the RINT
bit of CSR0.
Setting LAPPEN to a 1 also en-
ables the Am79C972 controller to
read the STP bit of receive de-
scriptors. The Am79C972 con-
troller
will
use
information to determine where it
should begin writing a receive
packet
’
s data. Note that while in
this mode, the Am79C972 con-
troller can write intermediate
packet data to buffers whose de-
scriptors do not contain STP bits
set to 1. Following the write to the
last descriptor used by a packet,
the Am79C972 controller will
scan through the next descriptor
entries to locate the next STP bit
that is set to a 1. The Am79C972
controller will begin writing the
next packets data to the buffer
pointed to by that descriptor.
the
STP
Note that because several de-
scriptors may be allocated by the
host for each packet, and not all
messages may need all of the de-
scriptors that are allocated be-
tween descriptors that contain
STP = 1, then some descriptors/
buffers may be skipped in the
ring. While performing the search
for the next STP bit that is set to
1, the Am79C972 controller will
advance through the receive de-
scriptor ring regardless of the
state of ownership bits. If any of
the entries that are examined
during
this
search
Am79C972 controller ownership
of the descriptor but also indicate
STP = 0, then the Am79C972
controller will reset the OWN bit
to 0 in these entries. If a scanned
entry indicates host ownership
with
STP = 0,
Am79C972 controller will not al-
ter the entry, but will advance to
the next entry.
indicate
then
the
When the STP bit is found to be
true, but the descriptor that con-
tains this setting is not owned by
the Am79C972 controller, then
the Am79C972 controller will stop
advancing through the ring en-
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C972BVD\\W 制造商:Advanced Micro Devices 功能描述:
AM79C972BVD\W 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 176-Pin TQFP Tray
AM79C972BVIW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C973 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C973/75 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Board Layout Considerations for the Am79C973/75 Network Interface? - (PDF)
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