參數(shù)資料
型號： AM79C972BVCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
中文描述： 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176
封裝： TQFP-176
文件頁數(shù)： 53/130頁
文件大?。?/td> 1580K
代理商： AM79C972BVCW
Am79C972
53
Figure 31.
16-Bit Software Model
Note that the value of CSR2, bits 15-8, is used as the
upper 8-bits for all memory addresses during bus mas-
ter transfers.
Figure 32 illustrates the relationship between the initial-
ization base address, the initialization block, the re-
ceive and transmit descriptor ring base addresses, the
receive and transmit descriptors, and the receive and
transmit data buffers, when SSIZE32 is set to 1.
Polling
If there is no network channel activity and there is no
pre- or post-receive or pre- or post-transmit activity
being performed by the Am79C972 controller, then the
Am79C972 controller will periodically poll the current
receive and transmit descriptor entries in order to as-
certain their ownership. If the TXDPOLL bit in CSR4 is
set, then the transmit polling function is disabled.
A typical polling operation consists of the following se-
quence. The Am79C972 controller will use the current
receive descriptor address stored internally to vector to
the appropriate Receive Descriptor Table Entry
(RDTE). It will then use the current transmit descriptor
address (stored internally) to vector to the appropriate
Transmit Descriptor Table Entry (TDTE). The accesses
will be made in the following order: RMD1, then RMD0
of the current RDTE during one bus arbitration, and
after that, TMD1, then TMD0 of the current TDTE dur-
ing a second bus arbitration. All information collected
during polling activity will be stored internally in the ap-
propriate CSRs, if the OWN bit is set (i.e., CSR18,
CSR19, CSR20, CSR21, CSR40, CSR42, CSR50,
CSR52).
A typical receive poll is the product of the following con-
ditions:
1. Am79C972 controller does not own the current
RDTE
and
the poll time has elapsed
and
RXON = 1 (CSR0, bit 5),
or
2. Am79C972 controller does not own the next RDTE
and
there is more than one receive descriptor in the
ring
and
the poll time has elapsed
and
RXON = 1.
Initialization
Block
MOD
PADR[15:0]
PADR[31:16]
PADR[47:32]
LADRF[15:0
LADRF[31:16]
LADRF[47:32]
LADRF[63:48]
RDRA[15:0]
RES
IADR[15:0]
IADR[31:16]
CSR1
CSR2
TDRA[15:0]
RES
RLE
RDRA[23:16]
TLE
TDRA[23:16]
Rcv
Buffers
RMD
RMD
RMD
RMD
Rcv Descriptor
Ring
N
N
N
N
1st
desc.
2nd
desc.
RMD0
Xmt
Buffers
TMD
TMD
TMD
TMD
Xmt Descriptor
Ring
M
M
M
M
1st
desc.
2nd
desc.
TMD
Data
Buffer
N
Data
Buffer
1
Data
Buffer
2
Data
Buffer
M
Data
Buffer
1
Data
Buffer
2
21485C-34
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