參數(shù)資料
型號(hào)： AM79C961AVCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁(yè)數(shù)： 97/206頁(yè)
文件大小： 1507K
代理商： AM79C961AVCW
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Am79C961A
97
MERR is set by the Bus Inter-
face Unit and cleared by writing
a
“
1". Writing a
“
0" has no effect.
MERR is cleared by RESET or
by setting the STOP bit.
Receive Interrupt is set after re-
ception of a receive frame and
toggling of the OWN bit in the
last buffer in the Receive
Descriptor Ring.
When RINT is set, IRQ is assert-
ed if IENA = 1 and the mask bit
RINTM (CSR3.10) is clear.
RINT is set by the Buffer Man-
agement Unit after the last
receive buffer has been updated
and cleared by writing a
“
1".
Writing a
“
0" has no effect. RINT
is cleared by RESET or by
setting the STOP bit.
Transmit Interrupt is set after
transmission of a transmit frame
and toggling of the OWN bit in
the last buffer in the Transmit
Descriptor Ring.
When TINT is set, IRQ is
asserted if IENA = 1 and the
mask bit TINTM (CSR3.9) is
clear.
TINT is set by the Buffer Man-
agement Unit after the last trans-
mit buffer has been updated and
cleared by writing a
“
1". Writing a
“
0" has no effect. TINT is cleared
by RESET or by setting the
STOP bit.
Initialization Done indicates that
the initialization sequence has
completed. When IDON is set,
PCnet-ISA II controller has read
the Initialization block from
memory.
When IDON is set, IRQ is assert-
ed if IENA = 1 and the mask bit
IDONM (CSR3.8) is clear.
IDON is set by the Buffer Man-
agement Unit after the initializa-
tion block has been read from
memory and cleared by writing a
“
1". Writing a
“
0" has no effect.
IDON is cleared by RESET or by
setting the STOP bit.
Interrupt Flag indicates that one
or more of the following interrupt
causing
conditions
occurred: BABL, MISS, MERR,
MPCO, RCVCCO, RINT, TINT,
IDON, JAB or TXSTRT; and its
associated mask bit is clear. If
10
RINT
9
TINT
8
IDON
7
INTR
has
IENA = 1 and INTR is set, IRQ
will be active.
INTR is cleared automatically
when the condition that caused
interrupt is cleared.
INTR is read only. INTR is
cleared by RESET or by setting
the STOP bit.
Interrupt Enable allows IRQ to
be active if the Interrupt Flag is
set. If IENA =
“
0" then IRQ will be
disabled regardless of the state
of INTR.
IENA is set by writing a
“
1" and
cleared by writing a
“
0". IENA is
cleared by RESET or by setting
the STOP bit.
Receive On indicates that the
Receive function is enabled.
RXON is set if DRX (CSR15.0) =
“
0" after the START bit is set. If
INIT and START are set togeth-
er, RXON will not be set until
after the initialization block has
been read in.
RXON is read only. RXON is
cleared by RESET or by setting
the STOP bit.
Transmit On indicates that the
Transmit function is enabled.
TXON is set if DTX (CSR15.1) =
“
0" after the START bit is set. If
INIT and START are set togeth-
er, TXON will not be set until
after the initialization block has
been read in.
TXON is read only. TXON is
cleared by RESET or by setting
the STOP bit.
Transmit Demand, when set,
causes the Buffer Management
Unit to access the Transmit
Descriptor Ring without waiting
for the poll-time counter to
elapse. If TXON is not enabled,
TDMD bit will be reset and no
Transmit Descriptor Ring access
will occur. TDMD is required to
be set if the DPOLL bit in CSR4
is set; setting TDMD while
DPOLL = 0 merely hastens the
PCnet-ISA II controller
’
s re-
sponse to a Transmit Descriptor
Ring Entry.
TDMD is set by writing a
“
1".
Writing a
“
0" has no effect.
TDMD will be cleared by the
Buffer Management Unit when it
fetches a Transmit Descriptor.
6
IENA
5
RXON
4
TXON
3
TDMD
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參數(shù)描述
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