參數(shù)資料
型號(hào)： AM79C961AVCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁(yè)數(shù)： 120/206頁(yè)
文件大?。?/td> 1507K
代理商： AM79C961AVCW
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120
Am79C961A
0
COL E
Enable Collision Signal. Indi-
cates collision activity on the
network.
0 disables the signal, 1 enables
the signal.
ISACSR8: Software Configuration Register
(Read-Only Register)
ISACSR9: Miscellaneous Configuration 2
Bit
Name
Description
1
AUIFD
AUI Full Duplex. AUIFD controls
whether Full Duplex operation
on the AUI port is enabled.
AUIFD is only meaningful if
FDEN (ISACSR9, bit 0) is set to
ONE. If the FDEN bit is ZERO,
the AUI port will always operate
in Half Duplex mode. In addition,
if FDEN is set to ONE but the
AUIFD bit is reset to ZERO, the
AUI port will always operate in
Half Duplex mode. If FDEN is set
to ONE and AUIFD is set to
ONE, Full Duplex operation on
the AUI port is enabled.
AUIFD is read/write accessible
always. It is reset to ZERO by
the RESET pin, and is unaffect-
ed by reading the Reset register
or setting the STOP bit.
Full Duplex Enable. FDEN con-
trols whether Full Duplex opera-
tion is enabled. When FDEN is
cleared, Full Duplex operation
is not enabled and the PC-
net-ISA II will always operate in
the Half Duplex mode. When
FDEN is set, the PCnet-ISA II
will operate in Full Duplex mode
when the 10BASE-T or GPSI
port is enabled or when the AUI
port is enabled and the AUIFD
(ISACSR9, bit 1) bit is set. Note
0
FDEN
that Full Duplex operation will
not
be
enabled
10BASE-T port if DLNKST
(CSR15, bit 12) is set.
FDEN is read/write accessible
always. It is reset to ZERO by
the RESET pin, and is unaffect-
ed by reading the Reset register
or setting the STOP bit.
on
the
Initialization Block
The figure below shows the Initialization Block memory
configuration. Note that the Initialization Block must be
based on a word (16-bit) boundary.
RLEN and TLEN
The TLEN and RLEN fields in the initialization block are
3 bits wide, occupying bits 15,14, and 13, and the value
in these fields determines the number of Transmit and
Receive Descriptor Ring Entries (DRE) which are used
in the descriptor rings. Their meaning is as follows:
If a value other than those listed in the above table is
desired, CSR76 and CSR78 can be written after initializa-
tion is complete. See the description of the appropriate
CSRs.
Bit
Description
15-12
Read-only image of SRAM(3:0) of PnP register
0x48-0x49.
11-8
Read-only image of BPAM(3:0) of PnP register
0x40-0x41.
7-4
Read-only image of IRQSEL(3:0) of PnP
register 0x70.
3
Read only bit indicating whether the SRAM is
activated as a
memory
resource. Set when the
Shared Memory is not activated as an ISA
memory resource.
2-0
Read-only image of DMASEL(2:0) of PnP
register 0x74.
Address
Bits
15
–
12
Bits
11
–
8
Bits
7
–
4
Bits
3
–
0
IADR+00
MODE 15
–
00
IADR+02
PADR 15
–
00
IADR+04
PADR 31
–
16
IADR+06
PADR 47
–
32
IADR+08
LADRF 15
–
00
IADR+10
LADRF 31
–
16
IADR+12
LADRF 47
–
32
IADR+14
LADRF 63
–
48
IADR+16
RDRA 15
–
00
IADR+18
RLEN
RES
RDRA 23
–
16
IADR+20
TDRA 15
–
00
IADR+22
TLEN
RES
TDRA 23
–
16
R/TLEN
# of DREs
000
1
001
2
010
4
011
8
100
16
101
32
110
64
111
128
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C961AVI 制造商:Rochester Electronics LLC 功能描述:
AM79C961AVI/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C961AVI\\W 制造商:Rochester Electronics LLC 功能描述:
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