參數(shù)資料
型號(hào)： AM79C961AVCW
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁(yè)數(shù)： 103/206頁(yè)
文件大小： 1507K
代理商： AM79C961AVCW
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Am79C961A
103
Read/write
when STOP or SPND bits are
set.
accessible
only
CSR12: Physical Address Register, PADR[15:0]
Bit
Name
Description
15-0 PADR[15:0]
Physical
PADR[15:0]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
Read/write
accessible
when STOP or SPND bits are
set.
Address
Register,
only
CSR13: Physical Address Register, PADR[31:16]
Bit
Name
Description
15-0PADR[31:16]
Physical
PADR[31:16]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
Read/write
accessible
when STOP or SPND bits are
set.
Address
Register,
only
CSR14: Physical Address Register, PADR[47:32]
Bit
Name
Description
15-0 PADR[47:32]
Physical
PADR[47:32]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
Read/write
accessible
when STOP or SPND bits are
set.
Address
Register,
only
CSR15: Mode Register
Bit
Name
Description
This register
’
s fields are loaded
during the PCnet-ISA II controller
initialization routine with the cor-
responding Initialization Block
values. The register can also be
loaded directly by an I/O write.
Activating the RESET pin clears
all bits of CSR15 to zero.
Promiscuous Mode.
When PROM =
“
1", all incoming
receive frames are accepted.
Read/write
accessible
when STOP or SPND bits are
set.
DisableReceiveBroadcast
.
When set, disables the PCnet-ISA
II controller from receiving broad-
cast messages. Used for proto-
cols that do not support broadcast
addressing, except as a function
of multicast. DRCVBC is cleared
by activation of the RESET pin
(broadcast messages will be
received).
Read/write
accessible
when STOP or SPND bits are
set.
Disable Receive Physical Ad-
dress. When set, the physical
address detection (Station or
node ID) of the PCnet-ISA II con-
troller will be disabled. Frames
addressed
to
individual physical address will
not be recognized (although the
frame may be accepted by the
EADI mechanism).
Read/write
accessible
when STOP or SPND bits are
set.
Disable Link Status. When
DLNKTST =
“
1", monitoring of
Link Pulses is disabled. When
DLNKTST =
“
0", monitoring of
Link Pulses is enabled. This bit
only has meaning when the
10BASE-T network interface is
selected.
Read/write
accessible
when STOP or SPND bits are
set.
Disable
Automatic
Correction. When DAPC =
“
1",
the 10BASE-T receive polarity
reversal algorithm is disabled.
Likewise, when DAPC =
“
0", the
polarity reversal algorithm is
enabled.
This bit only has meaning when
the 10BASE-T network interface
is selected.
Read/write
accessible
when STOP or SPND bits are
set.
15
PROM
only
14
DRCVBC
only
13
DRCVPA
the
nodes
only
12
DLNKTST
only
11
DAPC
Polarity
only
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參數(shù)描述
AM79C961AVI 制造商:Rochester Electronics LLC 功能描述:
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