參數(shù)資料
型號(hào)： AM79C961AVCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁(yè)數(shù)： 123/206頁(yè)
文件大?。?/td> 1507K
代理商： AM79C961AVCW
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Am79C961A
123
unchanged by the PCnet-ISA II
controller.
BUFFER BYTE COUNT is the
length of the buffer pointed to by
this descriptor, expressed as the
two
’
s complement of the length
of the buffer. This field is written
by the host and is not changed
by the PCnet-ISA II controller.
11-0
BCNT
RMD3
Bit
Name
Description
15-12
11-0
RES
MCNT
RESERVED and read as zeros.
MESSAGE BYTE COUNT is the
length in bytes of the received
message, expressed as an un-
signed binary integer. MCNT is
valid only when ERR is clear and
ENP is set. MCNT is written by
the PCnet-ISA II controller and
cleared by the host.
MCNT Includes: DEST + SRC +
Length + Data + CRC unless the
auto strip on receive bit is set. In
this case, the Pad and CRC are
thrown away by the controller.
Transmit Descriptors
The Transmit Descriptor Ring Entries (TDREs) are
composed of four transmit message fields (TMD0-3).
Together they contain the following information:
I
The address of the actual message data buffer in
user or host memory
I
The length of the message buffer
I
Status information indicating the condition of the
buffer. The eight most significant bits of TMD1
(TMD1[15:8]) are collectively termed the STATUS
of the transmit descriptor.
Note that bit 13 of TMD1, which was formerly a
reserved bit in the LANCE (Am7990), is assigned a
new meaning, ADD_FCS.
TMD0
Holds LADR [15:0]. This is combined with HADR [7:0]
in TMD1 to form a 24-bit address of the buffer pointed
to by this descriptor table entry. There are no restric-
tions on buffer byte alignment or length.
TMD1
Bit
Name
Description
15
OWN
This bit indicates that the
descriptor entry is owned by the
host (OWN=0) or by the PC-
net-ISA II controller (OWN=1).
The host sets the OWN bit after
filling the buffer pointed to by the
descriptor entry. The PCnet-ISA
II controller clears the OWN bit
after transmitting the contents of
the buffer. Both the PCnet-ISA II
controller and the host must not
alter a descriptor entry after it
has relinquished ownership.
ERR is the OR of UFLO, LCOL,
LCAR, or RTRY. ERR is written
by the PCnet-ISA II controller.
This bit is set in the current de-
scriptor when the error occurs,
and therefore may be set in any
descriptor of a chained buffer
transmission.
ADD_FCS dynamically controls
the generation of FCS on a
frame by frame basis. It is valid
only if the STP bit is set. When
ADD_FCS is set, the state of
DXMTFCS is ignored and trans-
mitter FCS generation is activat-
ed. When ADD_FCS = 0, FCS
generation is controlled by
DXMTFCS. ADD_FCS is written
by the host, and unchanged by
the PCnet-ISA II controller. This
was a reserved bit in the LANCE
(Am7990).
MORE indicates that more than
one re-try was needed to trans-
mit a frame. MORE is written by
the PCnet-ISA II controller. This
bit has meaning only if the ENP
or the ERR bit is set.
ONE indicates that exactly one
re-try was needed to transmit a
frame. ONE flag is not valid
when LCOL is set. ONE is writ-
ten by the PCnet-ISA II control-
ler. This bit has meaning only if
the ENP or the ERR bit is set.
DEFERRED indicates that the
PCnet-ISA II controller had to
defer while trying to transmit a
frame. This condition occurs if
the channel is busy when the
PCnet-ISA II controller is ready
to transmit. DEF is written by the
PCnet-ISA II controller. This bit
has meaning only if the ENP or
ERR bits are set.
14
ERR
13
ADD_FCS
12
MORE
11
ONE
10
DEF
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參數(shù)描述
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