- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C961AVCW (ADVANCED MICRO DEVICES INC) PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA PDF資料下載
參數(shù)資料
| 型號： | AM79C961AVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 129/206頁 |
| 文件大?。?/td> | 1507K |
| 代理商： | AM79C961AVCW |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁當(dāng)前第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁
Am79C961A
129
SYSTEM APPLICATION
ISA Bus Interface
Compatibility Considerations
Although 8 MHz is now widely accepted as the standard
speed at which to run the ISA bus, many machines have
been built which operate at higher speeds with non-stan-
dard timing. Some machines do not correctly support
16-bit I/O operations with wait states. Although the PC-
net-ISA II controller is quite fast, some operations still re-
quire an occasional wait state. The PCnet-ISA II
controller moves data through memory accesses, there-
fore, I/O operations do not affect performance. By con-
figuring the PCnet-ISA II controller as an 8-bit I/O device,
compatibility with PC/AT-class machines is obtained at
virtually no cost in performance. To treat the PCnet-ISA
II controller as an 8-bit software resource (for non-ISA
applications), the even-byte must be accessed first,
followed by an odd-byte access.
Memory cycle timing is an area where some tradeoffs
may be necessary. Any slow down in a memory cycle
translates directly into lower bandwidth. The PC-
net-ISA II controller starts out with much higher band-
width than most slave type controllers and should
continue to be superior even if an extra 50 or 100 ns
are added to memory cycles.
The memory cycle active time is tunable in 50 ns incre-
ments with a default of 250 ns. The memory cycle idle
time defaults to 200 ns and can be reprogrammed to
100 ns. See register description for ISACS42. Most
machines should not need tuning.
The PCnet-ISA II controller is compatible with NE2100
and NE1500T software drivers. All the resources such
as address PROM, boot PROM, RAP, and RDP are in
the same location with the same semantics. An addi-
tional set of registers (ISA CSR) is available to config-
ure on board resources such as ISA bus timing and
LED operation. However, loopback frames for the PC-
net-ISA II controller must contain more than 64 bytes of
data if the Runt Packet Accept feature is not enabled;
this size limitation does not apply to LANCE (Am7990)
based boards such as the NE2100 and NE1500T.
Bus Master
Bus Master mode is the preferred mode for client appli-
cations on PC/AT or similar machines supporting 16-bit
DMA with its unsurpassed combination of high perfor-
mance and low cost.
Shared Memory
The shared memory mode is recommended for file
servers or other applications where there is very high,
average or peak latency.
The address compare circuit has the following func-
tions. It receives the 7 LA signals, generates
MEMCS16, and compares them to the desired shared
memory and boot PROM addresses. The logic latches
the address compare result when BALE goes inactive
and uses the appropriate SA signals to generate
SMAM and BPAM.
All these functions can be performed in one PAL
device. To operate in an 8-bit PC/XT environment, the
LA signals should have weak pull-down resistors con-
nected to them to present a logic 0 level when not
driven.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C961AVIW | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| Am79C965A | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| AM79C970AKCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961AVI | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVI/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C961AVI\\W | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVI\W | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVIW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。