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參數(shù)資料
| 型號： | AM79C961AVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 68/206頁 |
| 文件大?。?/td> | 1507K |
| 代理商： | AM79C961AVCW |
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Am79C961A
ing intervals. All information collected during polling
activity will be stored internally in the appropriate
CSRs. (i.e. CSR18
–
19, CSR40, CSR20
–
21, CSR42,
CSR50, CSR52). Unowned descriptor status will be
internally ignored.
A typical receive poll occurs under the following
conditions:
1. PCnet-ISA II controller does not possess ownership
of the current RDTE and
the poll time has elapsed and
RXON = 1,
or
2. PCnet-ISA II controller does not possess ownership
of the next RDTE and
the poll time has elapsed and
RXON = 1,
If RXON = 0, the PCnet-ISA II controller will never poll
RDTE locations.
If RXON = 1, the system should always have at least
one RDTE available for the possibility of a receive
event. When there is only one RDTE, there is no polling
for next RDTE.
A typical transmit poll occurs under the following
conditions:
1. PCnet-ISA II controller does not possess ownership
of the current TDTE and
DPOLL = 0 and
TXON = 1 and
the poll time has elapsed,
or
2. PCnet-ISA II controller does not possess ownership
of the current TDTE and
DPOLL = 0 and
TXON = 1 and
a packet has just been received,
or
3. PCnet-ISA II controller does not possess ownership
of the current TDTE and
DPOLL = 0 and
TXON = 1 and
a packet has just been transmitted.
The poll time interval is nominally defined as 32,768
crystal clock periods, or 1.6 ms. However, the poll time
register is controlled internally by microcode, so any
other microcode controlled operation will interrupt the
incrementing of the poll count register. For example,
when a receive packet is accepted by the PCnet-ISA II
controller, the device suspends execution of the
poll-time-incrementing microcode so that a receive
microcode routine may instead be executed.
Poll-time-incrementing code is resumed when the
receive operation has completely finished. Note, how-
ever, that following the completion of any receive or
transmit operation, a poll operation will always be per-
formed. The poll time count register is never reset.
Note that if a non-default is desired, then a strict se-
quence of setting the INIT bit in CSR0, waiting for the
IDON bit in CSR0, then writing to CSR47, and then set-
ting STRT in CSR0 must be observed, otherwise the
default value will not be overwritten. See the CSR47
section for details.
Setting the TDMD bit of CSR0 will cause the microcode
controller to exit the poll counting code and immedi-
ately perform a polling operation. If RDTE ownership
has not been previously established, then an RDTE
poll will be performed ahead of the TDTE poll.
Transmit Descriptor Table Entry (TDTE)
If, after a TDTE access, the PCnet-ISA II controller
finds that the OWN bit of that TDTE is not set, then the
PCnet-ISA II controller resumes the poll time count and
re-examines the same TDTE at the next expiration of
the poll time count.
If the OWN bit of the TDTE is set, but STP = 0, the PC-
net-ISA II controller will immediately request the bus in
order to reset the OWN bit of this descriptor; this con-
dition would normally be found following a LCOL or
RETRY error that occurred in the middle of a transmit
packet chain of buffers. After resetting the OWN bit of
this descriptor, the PCnet-ISA II controller will again
immediately request the bus in order to access the next
TDTE location in the ring.
If the OWN bit is set and the buffer length is 0, the OWN
bit will be reset. In the LANCE the buffer length of 0 is
interpreted as a 4096-byte buffer. It is acceptable to
have a 0 length buffer on transmit with STP=1 or
STP=1
and
ENP = 1. It is not acceptable to have 0
length buffer with STP = 0
and
ENP = 1.
If the OWN bit is set and the start of packet (STP) bit is
set, then microcode control proceeds to a routine that
will enable transmit data transfers to the FIFO.
If the transmit buffers are data chained (ENP = 0 in the
first buffer), then the PCnet-ISA II controller will look
ahead to the next transmit descriptor after it has per-
formed at least one transmit data transfer from the first
buffer. More than one transmit data transfer may possi-
bly take place, depending upon the state of the trans-
mitter. The transmit descriptor look ahead reads TMD0
first and TMD1 second. The contents of TMD0 and
TMD1 will be stored in Next TX Descriptor Address
(CSR32), Next TX Byte Count (CSR66) and Next TX
Status (CSR67) regardless of the state of the OWN bit.
This transmit descriptor lookahead operation is
performed only once.
If the PCnet-ISA II controller does not own the next
TDTE (i.e. the second TDTE for this packet), then it will
complete transmission of the current buffer and then
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相關(guān)代理商/技術(shù)參數(shù) |
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| AM79C961AVI | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVI/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C961AVI\\W | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVI\W | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVIW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
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