- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C961AKIW (ADVANCED MICRO DEVICES INC) PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C961AKIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁(yè)數(shù)： | 18/206頁(yè) |
| 文件大?。?/td> | 1507K |
| 代理商： | AM79C961AKIW |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)當(dāng)前第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)
18
Am79C961A
PIN DESCRIPTION: BUS MASTER MODE
These pins are part of the bus master mode. In order to
understand the pin descriptions, definition of some
terms from a draft of IEEE P996 are included.
IEEE P996 Terminology
Alternate Master
: Any device that can take control of
the bus through assertion of the MASTER signal. It has
the ability to generate addresses and bus control sig-
nals in order to perform bus operations. All Alternate
Masters must be 16 bit devices and drive
SBHE
.
Bus Ownership
: The Current Master possesses bus
ownership and can assert any bus control, address and
data lines.
Current Master
: The Permanent Master, Temporary
Master or Alternate Master which currently has owner-
ship of the bus.
Permanent Master
: Each P996 bus will have a device
known as the Permanent Master that provides certain
signals and bus control functions as described in Sec-
tion 3.5 (of the IEEE P996 spec.),
“
Permanent Master
”
.
The Permanent Master function can reside on a Bus
Adapter or on the backplane itself.
Temporary Master
: A device that is capable of gener-
ating a DMA request to obtain control of the bus and
directly asserting only the memory and I/O strobes
during bus transfer. Addresses are generated by the
DMA device on the Permanent Master.
ISA Interface
AEN
Address Enable
This signal must be driven LOW when the bus performs
an I/O access to the device.
BALE
Used to latch the LA20
–
23 address lines.
DACK 3, 5-7
DMA Acknowledge
Asserted LOW when the Permanent Master acknowl-
edges a DMA request. When DACK is asserted the
PCnet-ISA II
controller becomes the Current Master by
asserting the MASTER signal.
DRQ 3, 5-7
DMA Request
When the PCnet-ISA II controller needs to perform a
DMA transfer, it asserts DRQ. The Permanent Master
acknowledges DRQ with the assertion of DACK. When
the PCnet-ISA II does not need the bus it desserts
DRQ. The PCnet-ISA II provides for fair bus bandwidth
sharing between two bus mastering devices on the ISA
bus through an adaptive delay which is inserted
Input
Input
Input/Output
between back-to-back DMA requests. See the
Back-to-Back DMA Requests section for details.
Because of the operation of the Plug and Play regis-
ters, the DMA Channels on the PCnet-ISA II must be
attached to the specific DRQ and DACK signals on the
PC/AT bus as indicated by the pin names.
IOCHRDY
I/O Channel Ready
When the PCnet-ISA II controller is being accessed,
IOCHRDY HIGH indicates that valid data exists on the
data bus for reads and that data has been latched for
writes. When the PCnet-ISA II controller is the Current
Master on the ISA bus, it extends the bus cycle as long
as IOCHRDY is LOW.
IOCS16
I/O Chip Select 16
When an I/O read or write operation is performed, the
PCnet-ISA II controller will drive the IOCS16 pin LOW
to indicate that the chip supports a 16-bit operation at
this address. (If the motherboard does not receive this
signal, then the motherboard will convert a 16-bit
access to two 8-bit accesses).
Input/Output
Output
The PCnet-ISA II controller follows the IEEE P996 spec-
ification that recommends this function be implemented
as a pure decode of SA0-9 and AEN, with no depen-
dency on IOR, or IOW; however, some PC/AT clone sys-
tems are not compatible with this approach. For this
reason, the PCnet-ISA II controller is recommended to
be configured to run 8-bit I/O on all machines. Since data
is moved by memory cycles there is virtually no perfor-
mance loss incurred by running 8-bit I/O and compatibil-
ity problems are virtually eliminated. The PCnet-ISA II
controller can be configured to run 8-bit-only I/O by
clearing Bit 0 in Plug and Play register F0.
IOR
I/O Read
IOR is driven LOW by the host to indicate that an Input/
Output Read operation is taking place. IOR is only valid
if the AEN signal is LOW and the external address
matches the PCnet-ISA II controller
’
s predefined I/O
address location. If valid, IOR indicates that a slave
read operation is to be performed.
IOW
I/O Write
IOW is driven LOW by the host to indicate that an Input/
Output Write operation is taking place. IOW is only valid
if AEN signal is LOW and the external address matches
the PCnet-ISA II controller
’
s predefined I/O address
location. If valid, IOW indicates that a slave write oper-
ation is to be performed.
Input
Input
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C961AVCW | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AVIW | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| Am79C965A | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| AM79C970AKCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961APDLUTS | 制造商:Advanced Micro Devices 功能描述: |
| AM79C961AVC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Advanced Micro Devices 功能描述:LAN Node Controller, 144 Pin, TQFP |
| AM79C961AVC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C961AVC\\W | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVC\W | 制造商:Rochester Electronics LLC 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。