參數(shù)資料
型號(hào)： AM79C961AKIW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132
封裝： PLASTIC, QFP-132
文件頁(yè)數(shù)： 100/206頁(yè)
文件大?。?/td> 1507K
代理商： AM79C961AKIW
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100
Am79C961A
back-off
implemented as described in the
Media
Access
section.
Read/Write accessible. EMBA is
cleared by RESET and is not
affected by STOP.
Reserved locations. Written as
zero and read as undefined.
algorithm
is
Management
2-0
RES
CSR4: Test and Features Control
Bit
Name
Description
15
ENTST
Enable Test Mode operation.
When ENTST is set, writing to
test mode registers CSR124 and
CSR126 is allowed, and other
register
test
enabled. In order to set ENTST, it
must be written with a
“
1" during
the first write access to CSR4
after RESET. Once a
“
0" is writ-
ten to this bit location, ENTST
cannot be set until after the PC-
net-ISA II controller is reset.
ENTST is cleared by RESET.
When DMAPLUS =
“
1", the burst
transaction counter in CSR80 is
disabled. If DMAPLUS =
“
0", the
burst transaction counter is
enabled.
Caution
: When using DMAPLUS
AND/OR TIMER bits in a PC
environment, care must be taken
not to hold the bus for more than
the required refresh time.
DMAPLUS is cleared by RESET.
Timer Enable Register. If TIMER
is set, the Bus Activity Timer reg-
ister (CSR82) is enabled and the
PCnet-ISA II may perform any
combination of accesses (buffer
reads, buffer writes, descriptor
reads, and descriptor writes)
during a single bus mastership
period. The bus is held until
either the Bus Activity Timer
expires or there are no further
pending operations to be per-
formed. The PCnet-ISA II deter-
mines whether there are further
pending bus operations by wait-
ing approximately 1
μ
s after the
completion of every bus opera-
tion (e.g. a descriptor or FIFO
access). If, during the 1
μ
s
period, no further bus operations
are requested by the internal
Buffer Management Unit, the
PCnet-ISA II determines that
functions
are
14
DMAPLUS
13
TIMER
there are no further pending
operations and gives up bus
ownership.
If TIMER is cleared, the Bus
Activity Timer register is dis-
abled and the PCnet-ISA II per-
forms only one type of access
(descriptor
read,
write, buffer read, or buffer
write) and buffer accesses are
performed
to
ascending addresses during
each bus mastership period.
TIMER is cleared by RESET.
Disable Transmit Polling. If
DPOLL is set, the Buffer Man-
agement Unit will disable trans-
mit polling. Likewise, if DPOLL is
cleared, automatic transmit poll-
ing is enabled. If DPOLL is set,
TDMD bit in CSR0 must be peri-
odically set in order to initiate a
manual poll of a transmit
descriptor. Transmit descriptor
polling will not take place if
TXON is reset.
DPOLL is cleared by RESET.
Auto Pad Transmit. When set,
APAD_XMT enables the auto-
matic padding feature. Transmit
frames will be padded to extend
them to 64 bytes, including FCS.
The FCS is calculated for the en-
tire frame (including pad) and
appended after the pad field.
APAD_XMT will override the
programming of the DXMTFCS
bit (CSR15.3).
APAD_ XMT is reset by activa-
tion of the RESET pin.
ASTRP_RCV enables the auto-
matic pad stripping feature. The
pad and FCS fields will be
stripped from receive frames
and not placed in the FIFO.
ASTRP_ RCV is reset by activa-
tion of the RESET pin.
Missed Frame Counter Overflow
Interrupt.
This bit indicates the MFC
(CSR112) has overflowed. Can
be cleared by writing a
“
1" to this
bit. Also cleared by RESET or
setting the STOP bit. Writing a
“
0" has no effect.
Missed Frame Counter Overflow
Mask.
If MFCOM is set, MFCO will not
set INTR in CSR0.
descriptor
adjacent
12
DPOLL
11
APAD_XMT
10 ASTRP_RCV
9
MFCO
8
MFCOM
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