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參數(shù)資料
| 型號： | AM79C961AKIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 114/206頁 |
| 文件大?。?/td> | 1507K |
| 代理商： | AM79C961AKIW |
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114
Am79C961A
ISA Bus Configuration Registers
The ISA Bus Data Port (IDP) allows access to registers
which are associated with the ISA bus. These registers
are called ISA Bus Configuration Registers (ISACSRs),
and are indexed by the value in the Register Address
Port (RAP). The table below defines the ISACSRs
which can be accessed. All registers are 16 bits. The
“
Default
”
value is the value in the register after reset
and is hexadecimal.Refer to the section
“
LEDs
”
for in-
formation on LED control logic.
ISACSR0: Master Mode Read Active/SRAM Data
Port
When in the Bus Master mode:
Bit
Name
Description
15-4
RES
Reserved locations. Written as
zero and read as undefined.
Master Mode Read Active time.
This register is used to tune the
MEMR command signal active
time when the PCnet-ISA II is in
the Bus Master mode. The value
stored in MSRDA defines the
number of 50 ns periods that the
command signal is active. The
default value of 5h indicates
250ns pulse widths. A value of 0
should not be used and may
result in no command assertion.
3-0
MSRDA
When in the Bus Slave, Programmed I/O architecture
mode:
15-0 SRAMDP
SRAM Data Port. This register
serves as a data port for access-
ing the SRAM when the PC-
net-ISA II is in the Bus Slave,
Programmed I/O architecture
mode. Accesses to this port are
directed to the SRAM location
that
is
addressed
SRAMAP register (ISACSR1).
Word
accesses
accesses to the even byte (least
significant bits) are allowed. Byte
accesses to the odd byte are not
allowed except when they are
performed
automatically
motherboard logic as discussed
in the Bus Cycles (Hardware)
section.
Read
accesses to this register will have
the side effect that the SRAMAP
register (ISACSR1) will incre-
ment by 1 or 2 depending on
whether a byte or word access,
respectively, is performed.
by
the
and
byte
by
and
write
ISACSR1: Master Mode Write Active/SRAM
Address Pointer
When in the Bus Master mode:
Bit
Name
Description
15-4
RES
Reserved locations. Written as
zero and read as undefined.
Master Mode Write Active time.
This register is used to tune the
MEMW command signal active
time when the PCnet-ISA II is in
the Bus Master mode. The value
stored in MSWRA defines the
number of 50 ns periods that the
command signal is active. The
default value of 5h indicates
250ns pulse widths. A value of 0
should not be used and may
result in no command assertion.
3-0
MSWRA
When in the Bus Slave, Programmed I/O architecture
mode:
15-0 SRAMAP
SRAM Address Pointer. This
register functions as an address
pointer for accessing the SRAM
when the PCnet-ISA II is in the
Bus Slave, Programmed I/O
architecture mode. Accesses to
the SRAMDP (ISACSR0) regis-
ter are directed to the SRAM
location that is addressed by this
register. This register is auto-
ISACSR
MNEMONIC
Default
Name
0
MSRDA
0005H
Master Mode
Read Active
1
MSWRA
0005H
Master Mode
Write Active
2
MC
0002H
Miscellaneous
Configuration
3
EC
8000H*
EEPROM
Configuration
4
LED0
0000H
Link Integrity
5
LED1
0084H
Default: RCV
6
LED2
0008H
Default:
RCVPOL
7
LED3
0090H
Default: XMT
8
SC
0000H
Software
Configuration
(Read-Only
register)
9
DUP
0000H
Default: Half
Duplex
This value can be 0000H for systems that do not support
EEPROM option.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961APDLUTS | 制造商:Advanced Micro Devices 功能描述: |
| AM79C961AVC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Advanced Micro Devices 功能描述:LAN Node Controller, 144 Pin, TQFP |
| AM79C961AVC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C961AVC\\W | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVC\W | 制造商:Rochester Electronics LLC 功能描述: |
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