參數(shù)資料
型號: ADS7870EA
英文描述: 12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM
中文描述: 12位ADC,復(fù)用器,PGA和內(nèi)部基準(zhǔn)數(shù)據(jù)采集系統(tǒng)
文件頁數(shù): 21/27頁
文件大?。?/td> 262K
代理商: ADS7870EA
21
ADS7870
|||{
{
|
A0
A1
A2
A3
A4
0
1
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Micro drives DIN
ADS7870 drives DIN
DIN high-impedance on inactive edge
SCLK
DIN
DOUT
CS
FIGURE 9. Timing for High Impedance State on DIN/DOUT (Inactive SCLK edge).
{
|||{
A0
A1
A2
A3
A4
0
1
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
SCLK
DIN
DOUT
CS
Micro drives DIN
ADS7870 drives DIN
DIN high-impedance on CS
FIGURE 8. Timing for High Impedance State on DIN/DOUT (CS = “1”).
Figures 8 and 9 show the timing of when the ADS7870 will
set the DIN pin to high impedance mode at the end of a read
operation when the 2W bit is set. The behavior of DOUT
does not depend of the state of 2W. The 8051 bit is not set
for these two examples.
Figure 10 shows the timing for entering the high impedance
state when the 8051 bit is set. Notice that on the last bit of
the read operation the DIN (and DOUT) pin goes to the high
impedance state on the active edge of SCLK instead of
waiting for the inactive edge of SCLK or CS going high as
shown in Figures 8 and 9. This is for compatibility with
80C51 Mode 0 type serial interfaces. An 80C51 forces DIN
valid before the SCLK falling edge and holds it valid until
after the SCLK rising edge. This can lead to contention but
setting the 8051 bit fixes this potential problem without
requiring CS to be toggled high after every read operation.
|||{
A0
A1
A2
A3
A4
0
1
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Micro drives DIN
ADS7870 drives DIN
DIN high-impedance on active SCLK edge
SCLK
DIN
DOUT
CS
FIGURE 10. Timing for High Impedance State on DIN/DOUT (8051 bit = “1”).
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