參數(shù)資料
型號: ADS7870EA
英文描述: 12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM
中文描述: 12位ADC,復(fù)用器,PGA和內(nèi)部基準(zhǔn)數(shù)據(jù)采集系統(tǒng)
文件頁數(shù): 18/27頁
文件大小: 262K
代理商: ADS7870EA
18
ADS7870
The four digital I/O pins allow control of external circuitry,
such as a multiplexer, or allow the digital status lines from
other devices to be read without using any additional micro-
controller pins. Reads from this register always reflect the
state of the pin, not the state of the latch inside the ADS7870.
These may be different if the pin(s) is configured as an input
or if there is a fault condition on an output pin(s).
Convert/Busy
If CNV/BSY is set to a “1” during a write operation, a
conversion will start on the second falling edge of CCLK
after the active edge of SCLK that latched the data into the
Digital I/O register. The CNV/BSY bit may be read with a
read instruction. The CNV/BSY will be set to “1” in a read
operation if the ADS7870 is performing a conversion at the
time the register is sampled in the read operation.
DIGITAL I/O CONTROL REGISTER
The Digital I/O Control register (ADDR = 6) contains the
information that determines whether each of the four digital
I/O lines is configured as an input or output. Setting the
appropriate OE bit to “1” enables the corresponding I/O pin
as an output. Setting the appropriate OE bit to “0” enables
the corresponding I/O pin as an input (see Table IX).
BIT
SYMBOL
NAME
VALUE
FUNCTION
D7
CNV/BSY
Convert/Busy
0
1
Idle Mode
Busy Mode; write = start conversion
D6-D4
G2-G0
PGA Gain Select
000
001
010
011
100
101
110
111
PGA Gain = 1
PGA Gain = 2
PGA Gain = 4
PGA Gain = 5
PGA Gain = 8
PGA Gain = 10
PGA Gain = 16
PGA Gain = 20
D3-D0
M3-M0
Input Channel Select
Table III
Determines input channel selection for the requested conversion,
differential or single-ended configuration.
Bold
items are power-up default conditions.
GAIN/MUX REGISTER
ADDR
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0
4
CNV/BSY
G2
G1
G0
M3
M2
M1
M0
TABLE VII. Gain/Mux Register (ADDR = 4).
ADDR = 4
BIT
SYMBOL
NAME
VALUE
FUNCTION
D7
CNV/BSY
Convert/Busy
0
1
Idle Mode
Busy Mode; Write = Start Conversion
D6-D4
0
These bits are not used and are always 0.
D3
IO3
State for I/O3
0
1
Input or Output State = 0
Input or Output State = 1
D2
IO2
State for I/O2
0
1
Input or Output State = 0
Input or Output State = 1
D1
IO1
State for I/O1
0
1
Input or Output State = 0
Input or Output State = 1
D0
IO0
State for I/O0
0
1
Input or Output State = 0
Input or Output State = 1
Bold
items are power-up default conditions.
NOTE: When the Mode Control makes a pin a Digital Input, it is not possible to control the state of the corresponding bit in the Digital I/O State register with
a write operation. The state of the bit is only controlled by the external signal connected to the Digital I/O pin.
DIGITAL I/O STATE REGISTER
ADDR
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0
5
CNV/BSY
0
0
0
IO3
IO2
IO1
IO0
TABLE VIII. Digital I/O State Register (ADDR = 5).
ADDR = 5
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