參數(shù)資料
型號(hào)： ADS7870EA
英文描述： 12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM
中文描述： 12位ADC，復(fù)用器，PGA和內(nèi)部基準(zhǔn)數(shù)據(jù)采集系統(tǒng)
文件頁(yè)數(shù)： 17/27頁(yè)
文件大小： 262K
代理商： ADS7870EA
17
ADS7870
A/D CONTROL REGISTER
The A/D Control register (ADDR = 3) configures the CCLK
divider and read back mode option as shown in
Table VI.
Read Back Modes
RBM1 and RBM0 determine which of four possible modes
is used to read the A/D conversion result from the A/D
Output registers.
Mode 0 (default mode) requires a separate read instruction
to be performed in order to read the output of the A/D
Output registers
Mode 1, 2, and 3 provide for different types of automatic
read-back options of the conversion results from the A/D
Output registers without having to use separate read in-
structions:
Mode 1: provides data MS byte first
Mode 2: provides data LS byte first
Mode 3: Output only the MS byte
For more information refer to the READ BACK MODE
section.
Clock Divider
CFD1 and CFD0 set the CCLK divisor constant which
determines the DCLK applied to the A/D, PGA and refer-
ence. The A/D and PGA operate with a maximum clock of
2.5MHz. In situations where an external clock is used to
pace the conversion process it may be desirable to reduce the
external clock frequency before it is actually applied to the
PGA and A/D. The signal that is actually applied to the
A/D and PGA is called DCLK, where DCLK = CCLK/DF
(DF is the division factor determined by the CFD1 and
CFD0 bits). For example, if the external clock applied to
CCLK is 10MHz and DF = 4 (CFD1 = 1, CFD0 = 0), DCLK
equals 2.5MHz.
GAIN/MUX REGISTER
The Gain/Mux register (ADDR = 4) contains the bits that
configure the PGA gain (G2-G0) and the input channel
selection (M3-M0) as shown in Table III. This register is
also updated when direct mode is used to start a conversion
so its bit definition is compatible with the instruction byte.
Input Channel Selection
Bits M3 through M0 configure the switches that determine
the input channel selection. The input channels may be
placed in either differential or single-ended configurations.
In the case of differential configuration, the polarity of the
input pins is reversible by the state of the M2 bit. The coding
for input channels is given in Table III and examples of
different input configurations are shown in Figure 7.
Convert/Busy
If the CNV/BSY bit is set to a “1” during a write operation,
a conversion will start on the second falling edge of CCLK
after the active edge of SCLK that latched the data into the
Gain/Mux register. The CNV/BSY bit may be read with a
read instruction. The CNV/BSY bit will bet set to “1” in a
read operation if the ADS7870 is performing a conversion at
the time the register is sampled in the read operation.
Gain Select
Bits G2 through G0 control the gain of the programmable
gain amplifier. PGA gains of 1, 2, 4, 5, 8, 10, 16 and 20 are
available. The coding is shown in Table VII.
DIGITAL INPUT/OUTPUT STATE REGISTER
The Digital I/O State register (ADDR = 5) contains the state
of each of the four digital I/O pins. Each pin can function as
a digital input (the state of the pin is set by an external signal
connected to it) or a digital output (the state of the pin is set
by data from a serial input to the ADS7870). The input/
output functional control is established by the digital I/O
mode control bits (OE3-OE0) in the Digital I/O Control
register. In addition, the convert/busy bit (CNV/BSY) can be
used to start a conversion via a write instruction or determine
if the converter is busy by executing a read instruction.
Digital I/O State Bits
Bits D3 through D0 (I/O3-I/O0) of the Digital I/O State
register are the state bits. If the corresponding mode bit
makes the pin a digital input, the state bit indicates whether
the external signal connected to the pin is a “1” or a “0”. It
is not possible to control the state of the corresponding bit
with a write operation. The state of the bit is only controlled
by the external signal connected to the digital I/O pin.
Coding is shown in Table VIII.
BIT
SYMBOL
NAME
VALUE
FUNCTION
D7-D4
—
—
0
These bits are reserved and must always be written 0.
D3-D2
RBM1-RBM0
Read Back
Mode
00
01
10
11
Mode 0 - Read instruction required to access ADC conversion result.
Mode 1 - Most significant byte returned first
Mode 2 - Least significant byte returned first
Mode 3 - Only most significant byte returned
D1-D0
CFD1-CFD0
CCLK Divide
00
01
10
11
Division factor for CCLK = 1 (DCLK = CCLK)
Division factor for CCLK = 2 (DCLK = CCLK/2)
Division factor for CCLK = 4 (DCLK = CCLK/4)
Division factor for CCLK = 8 (DCLK = CCLK/8)
Bold
items are power-up default conditions.
ADC CONTROL REGISTER
ADDR
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0
3
0
0
0
0
RBM1
RBM0
CFD1
CFD0
TABLE VI. ADC Control Register (ADDR = 3).
ADDR = 3
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS7870EA/1K 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit ADC MUX PGA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7870EA/1KG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit ADC MUX PGA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7870EA/250 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit
ADS7870EAG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit ADC MUX PGA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7870EVM 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS7870 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
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