參數(shù)資料
型號(hào): ADS7870EA
英文描述: 12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM
中文描述: 12位ADC,復(fù)用器,PGA和內(nèi)部基準(zhǔn)數(shù)據(jù)采集系統(tǒng)
文件頁數(shù): 15/27頁
文件大?。?/td> 262K
代理商: ADS7870EA
15
ADS7870
Figure 6 provides an example of a 16-bit read operation from
an odd address with LSB first and SCLK active on the rising
edge. The address (ADDR) for the second byte is decremented
by one since the ADDR in the instruction byte is odd. For an
even ADDR, the address for the second byte would be
incremented by one.
MULITPLEXER ADDRESSING
The last four bits in the Instruction Byte (during a start
conversion instruction) or the Gain/Mux Register (ADDR = 4)
z
|
CS
y
{
z
|
z
y
{
z
|
y
{
z
|
y
{
z
|
y
{
z
|
zy
|||
1
A1
A2
A3
A4
1
1
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Data from ADDR
Data from ADDR-1
SCLK
DOUT
FIGURE 6. Example Timing Diagram for a 16-Bit Read from an Odd Address.
FIGURE 7. Examples of Multiplexer Options.
EXAMPLES OF MULTIPLEXER OPTIONS
LN0, LN1
Channel
4 Differential
LN2, LN3
LN4, LN5
LN6, LN7
LN0, LN1
LN2, LN3
LN0
LN1
LN2
LN3
LN4
LN5
LN6
LN7
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Channel
8 Single-Ended
LN4
LN5
LN6
LN7
Channel
Differential and
Single-Ended
M3
M2
M1
M0
LN0
LN1
LN2
LN3
LN4
LN5
LN6
LN7
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+
+
+
+
+
+
+
+
Bit M3 selects either differential or single-ended mode.
If differential mode is selected, Bit M2 determines the polarity of the input channels.
Bold
items are power-up default conditions.
CODING FOR DIFFERENTIAL INPUT CHANNEL SELECT
SELECTION BITS
INPUT LINES
M3
M2
M1
M0
LN0
LN1
LN2
LN3
LN4
LN5
LN6
LN7
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+
+
+
+
+
+
+
+
CODING FOR SINGLE-ENDED INPUT CHANNEL SELECT (negative input is ground)
SELECTION BITS
INPUT LINES
TABLE III. Multiplexer Addressing.
assign the mulitplexer configuration for the requested conver-
sion. The input channels may be placed in either differential
or single-ended configurations. For differential configura-
tions, the polarity of the input signal is reversible by the state
of M2 (Bit D2). In single-ended mode, all input channels are
measured with respect to system ground. Figure 7 shows
some examples of mulitplexer assignments and Table III
provides the coding for the input channel selection.
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