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參數(shù)資料
| 型號： | ADS7870EA |
| 英文描述： | 12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM |
| 中文描述： | 12位ADC，復(fù)用器，PGA和內(nèi)部基準(zhǔn)數(shù)據(jù)采集系統(tǒng) |
| 文件頁數(shù)： | 16/27頁 |
| 文件大?。?/td> | 262K |
| 代理商： | ADS7870EA |
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16
ADS7870
INTERNAL USER-ACCESSIBLE
REGISTERS
The registers in the ADS7870 are eight bits wide. Most of
the registers are reserved, the ten user-accessible registers
are summarized in the Register Address Map (Table I).
Detailed information for each register follows. The default
power-on/reset state of all bits in the registers is “0”.
ADC OUTPUT REGISTERS
The A/D Output registers are read only registers located at
ADDR = 0 and ADDR = 1 that contain the results of the
A/D conversion, ADC11 through ADC0 (Table IV). The
conversion result is in 2’s complement format. The bits can
be taken out of the registers MSB (D7) first or LSB (D0)
first, as determined by the state of the LSB bits (D7 and D0)
in the Serial Interface Control register. The ADDR = 0
register also contains the OVR bit which indicates if the
internal voltage limits to the PGA have been exceeded.
PGA VALID REGISTER
The PGA Valid register (ADDR = 2) is a read only register
that contains the individual results of each of the six com-
parators for the PGA, VLD5 through VLD0, as shown in
Table V.
BIT
SYMBOL
NAME
VALUE
FUNCTION
D7-D6
—
—
0
These bits are not used and are always 0.
D5
VLD5
PGA Valid 5
0
1
Voltage at “–” output from the PGA has exceeded its minimum value.
D4
VLD4
PGA Valid 4
0
1
Voltage at “–” output from the PGA has exceeded its maximum value.
D3
VLD3
PGA Valid 3
0
1
Voltage at “–” input to the PGA has exceeded its allowable value.
D2
VLD2
PGA Valid 2
0
1
Voltage at “+” output from the PGA has exceeded its minimum value.
D1
VLD1
PGA Valid 1
0
1
Voltage at “+” output from the PGA has exceeded its maximum value.
D0
VLD0
PGA Valid 0
0
1
Voltage at “+” input to the PGA has exceeded its allowable value.
ADDR = 0 (LS Byte)
BIT
SYMBOL
NAME
VALUE
FUNCTION
D7-D4
ADC3-ADC0
A/D Output
(1)
Four least significant bits of conversion result.
D3-D1
—
—
0
These bits are not used and are always 0.
D0
OVR
PGA Over-Range
0
Valid conversion result
1
An analog over-range problem has occurred in the PGA. Conver-
sion result may be invalid. Details of the type of problem are stored
in Register 2, the PGA Valid register.
ADC OUTPUT REGISTERS
ADDR
D7(MSB)
D6
D5
D4
D3
D2
D1
D0
0
ADC3
ADC2
ADC1
ADC0
0
0
0
OVR
1
ADC11
ADC10
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
NOTE: (1) Value depends on conversion result.
ADDR = 1 (MS Byte)
BIT
SYMBOL
NAME
VALUE
FUNCTION
D7-D0
ADC11-ADC4
ADC Output
(1)
Eight most significant bits of conversion result.
TABLE IV. ADC Output Registers (ADDR = 0 and ADDR = 1).
PGA VALID REGISTER
ADDR
D7(MSB)
D6
D5
D4
D3
D2
D1
D0
2
0
0
VLD5
VLD4
VLD3
VLD2
VLD1
VLD0
TABLE V. PGA Valid Register (ADDR = 2).
ADDR = 2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7870EA/1K | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit ADC MUX PGA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7870EA/1KG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit ADC MUX PGA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7870EA/250 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit |
| ADS7870EAG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit ADC MUX PGA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7870EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS7870 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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