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參數(shù)資料
| 型號： | ADS7870EA |
| 英文描述： | 12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM |
| 中文描述： | 12位ADC，復用器，PGA和內部基準數(shù)據采集系統(tǒng) |
| 文件頁數(shù)： | 13/27頁 |
| 文件大?。?/td> | 262K |
| 代理商： | ADS7870EA |
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13
ADS7870
In addition, registers 4 and 5 contain a convert/busy bit
(CNV/BSY) that can be used to start a conversion via a write
instruction or sense when the converter is busy with a read
instruction.
Register 6, the Digital I/O Control Register, contains the
information that determines whether each of the four digital
I/O pins is to be an input or an output function (OE3 through
OE0). This sets the mode of each I/O pin.
Register 7, the Ref/Oscillator Control Register, controls
whether the internal oscillator used for the conversion clock
is on or off (OSCE), whether the internal voltage reference
and buffer are on or off (REFE, BUFE), and whether the
reference provides 2.5V, 2.048V, or 1.15V.
Register 24, the Serial Interface Control Register, controls
whether data is presented MSB or LSB first (LSB bit),
whether the serial interface is configured for 2-wire or 3-
wire operation (2W bit), and determines proper timing
control for 8051-type microprocessor interfaces (8051 bit).
Reset
In the event that system synchronization is lost between the
ADS7870 and its controller there are three ways to reset.
The entire register contents as well as the serial interface are
reset on:
1) Cycle power. The power down time must be long enough
to allow internal nodes to discharge.
2) Toggle the RESET pin. Minimum pulse width to reset is
50 ns.
3) Write an 8-bit byte of all zeros to register 0.
All of these actions set all internal registers to zero. This turns
off the oscillator and reference. Recovery time is dependent on
the size of the filter capacitor in the reference output.
If the serial interface is synchronized and waiting for an
instruction then eight cycles of the SCLK with DIN zero
followed by a single “1” will reset the device. The next active
edge of SCLK following the “1” is the first bit of the next
instruction. Cycling CS will assure that the serial interface is
reset.
The serial interface is resynchronized every time the CS signal
is “1”. For this reason it is mandatory that CS be held low
throughout any communication sequence with the ADS7870.
This synchronization does not change any of the register
values.
For those instances where CS cannot be cycled it is necessary
to write thirty-nine “0”s followed by a “1”. This string length
is based on the worst case conditions to ensure that the device
is synchronized.
WRITE OPERATION
To perform a write operation an instruction byte must first
be written to the ADS7870 as described previously (see
Table I). This instruction will determine the target register as
well as the word length (8 bits or 16 bits). The CS pin must
be asserted (“0”) prior to the first active SCLK edge (rising
or falling depending on the state of the RISE/FALL pin) that
will latch the first bit of the instruction byte. The first active
edge after CS must have the first bit of the instruction byte.
The remaining seven bits of the instruction byte will be
latched on the next seven active edges of SCLK. CS must
remain low for the entire sequence. Setting CS high will
resynchronize the serial interface.
When starting a conversion by setting the CNV/BSY bit in
the Gain/Mux register and/or the Digital I/O register, the
conversion will start on the second falling edge of CCLK
after the last active SCLK edge of the write operation.
Figure 3 shows an example of an eight-bit write operation
with LSB first and SCLK active on the rising edge. The
double arrows indicate the SCLK transition when data is
latched into its destination register. Figure 4 shows an
example of the timing for a 16-bit write to an even address
with LSB first and SCLK active on the rising edge. Notice
that both bytes are updated to their respective registers
simultaneously. Also shown is that the address (ADDR) for
the write of the second byte is incremented by one since the
ADDR in the instruction byte was even. For an odd ADDR,
the address for the second byte would be ADDR-1.
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{
|
|
A0
A1
A2
A3
A4
0
0
0
D0
D1
D2
D3
D4
D5
D6
D7
SCLK
DIN
DOUT
CS
Register is updated
Instruction Latched
FIGURE 3. Example Timing Diagram for an 8-Bit Write Operation.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7870EA/1K | 功能描述:模數(shù)轉換器 - ADC 12-Bit ADC MUX PGA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7870EA/1KG4 | 功能描述:模數(shù)轉換器 - ADC 12-Bit ADC MUX PGA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7870EA/250 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit |
| ADS7870EAG4 | 功能描述:模數(shù)轉換器 - ADC 12-Bit ADC MUX PGA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7870EVM | 功能描述:數(shù)據轉換 IC 開發(fā)工具 ADS7870 Eval Mod RoHS:否 制造商:Texas Instruments 產品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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