
12
ADS7870
ADDR
N0.
READ/
WRITE
REGISTER
NAME
AS4
AS3
AS2
AS1
AS0
D7(MSB)
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
24
31
Read
Read
Read
R/W
R/W
R/W
R/W
R/W
R/W
Read
ADC3
ADC11
0
0
CNV/BSY
CNV/BSY
0
0
LSB
0
ADC2
ADC10
0
0
G2
0
0
0
2W/3
0
ADC1
ADC9
VLD5
0
G1
0
0
OSCR
8051
0
ADC0
ADC8
VLD4
0
G0
0
0
OSCE
0
0
0
0
0
OVR
ADC4
VLD0
CFD0
M0
IO0
OE0
RGB
LSB
1
A/D Output Data, LS Byte
A/D Output Data, MS Byte
PGA Valid Register
A/D Control Register
Gain/Mux Register
Digital I/O State Register
Digital I/O Control Register
Ref/Oscillator Control Register
Serial Interface Control
ID Register
ADC7
VLD3
RBM1
M3
IO3
OE3
REFE
0
0
ADC6
VLD2
RBM0
M2
IO2
OE2
BUFE
8501
0
ADC5
VLD1
CFD1
M1
IO1
OE1
R2V
2W/3
0
REGISTER ADDRESS
REGISTER ADDRESS
TABLE II. Register Address Map.
The structure of the instruction byte for direct mode is
shown in Table I.
D7: This bit is set to “1” for direct mode operation
D6 through D4 (G2-G0): These bits control the gain of the
programmable gain amplifier. PGA gains of 1, 2, 4, 5, 8, 10,
16 and 20 are available. The coding is shown in Table I.
D3 through D0 (M3-M0): These bits configure the switches
that determine the input channel selection. The input
channels may be placed in either differential or single
ended configurations. In the case of differential configu-
ration, the polarity of the input signal is reversible. The
coding is shown in Table III.
Note that the seven lower bits of this byte are written to
register 4, the Gain/Mux register.
All other controllable ADS7870 parameters are values pre-
viously stored in their respective registers. These values are
either the power-up default values or values that were
previously written to one of the control registers in an
Register mode operation. No additional data is required for
a direct mode instruction.
Register Mode
In register mode (Bit D7 of the Instruction Byte is “0”) a
read or write instruction to one of the ADS7870’s registers
is initiated. All of the user determinable functions and
features of the ADS7870 can be controlled by writing
information to these registers (see Table II). Conversion
results can be read from the A/D Output registers.
The Instruction Byte (see Table I) contains the address of the
register for the next read/write operation, determines whether
the serial communication is to be done in 8-bit or 16-bit
word length, and determines whether next operation will
read-from or write-to the addressed register.
The structure of the instruction byte for register mode is
shown in Table I.
D7: This bit is set to “0” for “register” mode operation.
D6 (R/W): Bit 6 of the Instruction Byte determines whether
a read or write operation is performed, “1” for a read or
“0” for a write.
D5 (16/8): This bit determines the word length of the read
or write operation that follows, “1” for sixteen bits (two
eight-bit bytes) or “0” for eight bits.
D4 through D0 (AS4-AS0): These bits determine the
address of the register that is to be read-from or written-
to. See Table II for register address coding and other
information.
For sixteen-bit operations, the first eight bits will be written-
to/read-from the address encoded by instruction byte, bits
AS4 through AS0 (Register Address). The address of the
next eight bits depends on whether the Register Address for
the first byte is odd or even. If it is even, then the address for
the second byte will be Register Address + 1. If the Register
Address is odd, then the address for the second byte is the
Register Address – 1.
This arrangement allows transfer of conversion results from
the two A/D Output Data registers either MS byte first or LS
byte first (see Serial Interface Control Register text).
Register Summary
A summary of information about the ADS7870 addressable
registers is shown in Table II. Brief descriptions of the ten
user-addressable registers follow. More detailed information
on the individual registers is provided in the INTERNAL
USER-ACCESSIBLE REGISTERS section.
Registers 0 and 1, the A/D output data registers, contain the
least significant and most significant bits (ADC0 through
ADC11) of the A/D conversion result. Register 0 also
contains a bit that indicates if the allowable internal voltage
limits for the PGA have been exceeded (OVR).
Register 2, the PGA Valid Register, contains information
that describes the nature of the problem in the event that the
allowable input voltage to the PGA has been exceeded.
Register 3, the A/D Control Register, contains information
regarding the serial interface; a frequency division factor
used for the conversion clock function (CDF0 and CDF1)
and configuration control of an automatic read back option
(RBM0 and RBM1).
Register 4, the Gain/Mux Register, contains the input chan-
nel selection information (M0 through M3) and the pro-
grammable gain amplifier gain set bits (G0 through G2).
Register 5, the Digital I/O State Register, contains the state
of each of the digital I/O pins (I/O3 through I/O0).