參數(shù)資料
型號(hào)： ADS7870EA
英文描述： 12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM
中文描述： 12位ADC，復(fù)用器，PGA和內(nèi)部基準(zhǔn)數(shù)據(jù)采集系統(tǒng)
文件頁(yè)數(shù)： 19/27頁(yè)
文件大?。?/td> 262K
代理商： ADS7870EA
19
ADS7870
REFERENCE/OSCILLATOR CONFIGURATION
REGISTER
The Reference/Oscillator Configuration register (ADDR = 7)
determines whether the internal oscillator is used for the
conversion clock (OSCE and OSCR), whether the internal
voltage reference and buffer are on or off (REFE and BUFE),
and whether the reference is 2.5V, 2.048V, or 1.15V as shown
in Table X.
Oscillator Control
The internal voltage reference uses a switched capacitor
technique which requires a clocking signal input. When
OSCR = 1, the clocking signal for the reference comes from
the internal oscillator. When OSCR = 0, the clocking signal
for the reference is derived from the signal on the CCLK pin
and affected by the frequency divider controlled by the
CFD0 and CFD1 bits in the A/D Control register.
The OSCE bit is the internal oscillator enable bit. When it is
set to “1” power is applied to the internal oscillator causing
it to produce a 2.5MHz output and causing the signal to
appear at the CCLK pin. The internal oscillator is also
enabled when the OSCR bit is set to “1” and the REFE bit
is also set to “1”.
The internal oscillator is also enabled when the OSC EN-
ABLE pin is set to “1”. The power-up default condition is
“0” for OSCE and OSCR. If either the OSC ENABLE pin is
held high or these control register bits are “1” then the
oscillator will be turned on.
Voltage Reference and Buffer Enable
When the REFE bit = “0” (power-up default condition), the
reference is powered down and draws no current. When it is
set to “1”, it is powered up and draws approximately 190
μ
A
of current.
When the BUFE bit = “0” (power-up default condition) the
buffer amplifier is powered down and draws no current.
When it is set to “1”, it is powered up and draws approxi-
mately 150
μ
A of current.
BIT
SYMBOL
NAME
VALUE
FUNCTION
D7-D4
—
—
0
These bits are reserved and must always be set to 0.
D3
OE3
State for I/O3
0
1
Digital I/O 1 = digital input
Digital I/O 1 = digital output
D2
OE2
State for I/O2
0
1
Digital I/O 2 = digital input
Digital I/O 2 = digital output
D1
OE1
State for I/O1
0
1
Digital I/O 3 = digital input
Digital I/O 3 = digital output
D0
OE0
State for I/O0
0
1
Digital I/O 4 = digital input
Digital I/O 4 = digital output
Bold
items are power-up default conditions.
DIGITAL I/O CONTROL REGISTER
ADDR
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0
6
0
0
0
0
OE3
OE2
OE1
IOE0
TABLE IX. Digital I/O Control Register (ADDR = 6).
ADDR = 6
BIT
SYMBOL
NAME
VALUE
FUNCTION
D7-D6
—
—
0
These bits are reserved and must always be set to 0.
D5
OSCR
Oscillator Control
0
1
Source of clock for internal V
is CCLK pin.
Clocking signal comes from the internal oscillator.
D4
OSCE
Oscillator Enable
0
1
CCLK is configured as an input.
CCLK outputs a 2.5MHz signal (70
μ
A).
Reference is powered down and draws no current.
Reference is powered up and draws 190
μ
A of current.
Buffer is powered down and draws no current.
Buffer is powered up and draws 150
μ
A of current.
V
REF
= 2.5V (RBG bit = 0)
V
REF
= 2.048V (RBG bit = 0)
Bit R2V determines the value of the reference voltage.
V
REF
= 1.15V
D3
REFE
Reference Enable
0
1
D2
BUFE
Buffer Enable
0
1
D1
R2V
2V Reference
0
1
D0
RBG
Bandgap Reference
0
1
Bold
items are power-up default conditions.
REFERENCE/OSCILLATOR REGISTER
ADDR
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0
7
0
0
OSCR
OSCE
REFE
BUFE
R2V
RBG
TABLE X. Reference/Oscillator Configuration Register (ADDR = 7).
ADDR = 7
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