參數(shù)資料
型號(hào)： AD9992BBCZRL
廠商： Analog Devices Inc
文件頁數(shù)： 6/92頁
文件大?。?/td> 0K
描述： IC CCD SGNL PROC 12BIT 105CSPBGA
產(chǎn)品變化通告： AD9992 Discontinuation 22/Feb/2012
標(biāo)準(zhǔn)包裝： 2,000
類型： CCD 信號(hào)處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 27mA
安裝類型： 表面貼裝
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 帶卷 (TR)
AD9992
Rev. C | Page 14 of 92
SYSTEM OVERVIEW
Figure 12 shows the typical system block diagram for the AD9992
in master mode. The CCD output is processed by AD9992 AFE
circuitry, which consists of a CDS, VGA, black level clamp, and
ADC. The digitized pixel information is sent to the digital
image processor chip, which performs the postprocessing and
compression. To operate the CCD, all CCD timing parameters
are programmed into the AD9992 from the system microprocessor
through the 3-wire serial interface. The AD9992 generates the
CCD’s horizontal and vertical clocks and internal AFE clocks
from the master clock, CLI, which is provided by the image
processor or external crystal,. External synchronization is provided
by a sync pulse from the microprocessor, which resets the
internal counters and resyncs the VD and HD outputs.
CCDIN
GPO1 TO GPO8
H1 TO H8, HL,
RG
XV1 TO XV24, XSUBCK
CCD
AD9992
AFETG
DIGITAL
IMAGE
PROCESSING
ASIC
DOUT
DCLK
HD, VD
CLI
SERIAL
INTERFACE
SYNC
MICROPROCESSOR
V-DRIVER
05
89
1-
01
2
Figure 12. Typical System Block Diagram, Master Mode
Alternatively, the AD9992 can operate in slave mode. In slave
mode, the VD and HD are provided externally from the image
processor, and all AD9992 timing synchronizes with VD and HD.
H-drivers for H1 to H8, HL, and RG are included in the AD9992,
allowing these clocks to be directly connected to the CCD.
An H-driver voltage of up to 3.3 V is supported. An external
V-driver is required for the vertical transfer clocks, the sensor
gate pulses, and the substrate clock.
The AD9992 includes programmable general-purpose outputs
(GPO), which can trigger mechanical shutter and strobe (flash)
circuitry.
Figure 13 and Figure 14 show the maximum horizontal and
vertical counter dimensions for the AD9992. All internal
horizontal and vertical clocking is controlled by these counters,
which specify line and pixel locations. Maximum HD length
is 8192 pixels per line; maximum VD length is 8192 lines per field.
13-BIT HORIZONTAL = 8192 PIXELS MAX
13-BIT VERTICAL = 8192 LINES MAX
MAXIMUM COUNTER DIMENSIONS
0
58
91
-01
3
Figure 13. Vertical and Horizontal Counters
VD
HD
MAX VD LENGTH IS 8192 LINES
CLI
MAX HD LENGTH IS 8192 PIXELS
0
589
1-
0
14
Figure 14. Maximum VD/HD Dimensions
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