- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1895 > AD9992BBCZRL (Analog Devices Inc)IC CCD SGNL PROC 12BIT 105CSPBGA PDF資料下載
參數(shù)資料
| 型號： | AD9992BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SGNL PROC 12BIT 105CSPBGA |
| 產(chǎn)品變化通告： | AD9992 Discontinuation 22/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 27mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
AD9992
Rev. C | Page 33 of 92
conserves register memory if the four separate V-patterns are
not needed.
Note that when CONCAT_GRP is enabled, Group A settings
are used only for start position, polarity, length, and repetitions.
All toggle positions for Group A, Group B, Group C, and Group D
are combined together and applied using the settings in the
VSTARTA, VPOL_A, VLENA, and VREPA registers.
Special Vertical Sequence Alternation (SVSA) Mode
The AD9992 has additional flexibility for combining four
different V-pattern groups in a random sequence that can be
programmed for specific CCD requirements. This mode of
operation allows custom vertical sequences for CCDs that
require more complex vertical timing patterns. For example,
using the special vertical sequence alternation mode, it is
possible to support random pattern concatenation, with
additional support for odd/even line alternation.
Figure 39 illustrates four common and repetitive vertical pattern
segments, A through D, that are derived from the complete vertical
pattern. Figure 40 illustrates how each group can be concatenated
in an arbitrary order.
To enable the SVSA mode, write the VSEQALT_EN bit,
Address 0x20 Bit 13, equal to 0x01. The location of the VALTSEL
registers is shared with the VPAT registers for XV24. When
SVSA mode is enabled, the VALTSEL register function is
selected.
To create SVSA timing, divide the complete vertical timing
pattern into four common and repetitive segments. Identify
the related segments as VPATA, VPATB, VPATC, or VPATD.
Up to four toggle positions for each segment can be programmed
using the V-pattern registers.
Table 15 shows how the segments are specified using a 2-bit
representation. Each bit from VALTSEL0 and VALTSEL1 is
combined to produce four values, corresponding to Pattern A,
Pattern B, Pattern C, and Pattern D.
Table 15. VALTSEL Bit Settings for Even and Odd Lines
Parameter
VALTSEL Bit Settings
VALTSEL0_EVEN
0
1
VALTSEL1_EVEN
0
1
0
1
VALTSEL0_ODD
0
1
VALTSEL1_ODD
0
1
0
1
Resulting pattern for even lines
A
B
C
D
Resulting pattern for odd lines
A
B
C
D
When the entire pattern is divided, program VALTSEL0 (even
and odd) [17:0] and VALTSEL1 (even and odd) [17:0] so that
the segments are concatenated in the desired order. If separate
odd and even lines are not required, set the odd and even registers
to the same value. Figure 41 illustrates the process of using six
vertical pattern segments that have been concatenated into a small,
merged pattern.
Program the register VREPA_1 to specify the number of segments
to concatenate into each merged pattern. The maximum number of
segments that can be concatenated to create a merged pattern is
18. Program VLENA, VLENB, VLENC, VLEND to be of equal
length. Finally, program HBLK to generate the proper H-clock
timing using the procedure for HBLK Mode 2 described in the
HBLK Mode 2 Operation section.
It is important to note that because the FREEZE/RESUME registers
are used to specify the VALTSEL registers, the VALT_MAP
register must be enabled when using the special VALT mode.
Table 16. VALTSEL Register Locations1
Register Function
When VSEQALT_EN = 1
Register Location
VALTSEL0_EVEN [12:0]
VSEQ register FREEZE1 [12:0]
VALTSEL0_EVEN [17:13]
VSEQ register RESUME1 [17:13]
VALTSEL1_EVEN [12:0]
VSEQ register FREEZE2 [12:0]
VALTSEL1_EVEN [17:13]
VSEQ register RESUME2 [17:13]
VALTSEL0_ODD [12:0]
VSEQ register FREEZE3 [12:0]
VALTSEL0_ODD [17:13]
VSEQ register RESUME3 [17:13]
VALTSEL1_ODD [12:0]
VSEQ register FREEZE4 [12:0]
VALTSEL1_ODD [17:13]
VSEQ register RESUME4 [17:13]
1 The VALT_MAP register must be set to 1 to enable the use of VALTSEL
registers.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9995KCPZ | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| ADA4424-6ARUZ | IC FILTR VID6CH SD/ED/HD 38TSSOP |
| ADATE302-02BBCZ | IC DCL ATE 500MHZ DUAL 84CSPBGA |
| ADATE304BBCZ | IC DCL ATE 200MHZ DUAL 84CSPBGA |
| ADATE305BSVZ | IC DCL ATE 250MHZ DUAL 100TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1,500 |
| AD9993-EBZ | 功能描述:EVAL BOARD MXFE AD9993 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1 |
| AD9994 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9994BCP | 制造商:Analog Devices 功能描述:AFE GEN PURPOSE 12-BIT 64LFCSP - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。