參數(shù)資料
型號: AD9992BBCZRL
廠商: Analog Devices Inc
文件頁數(shù): 55/92頁
文件大?。?/td> 0K
描述: IC CCD SGNL PROC 12BIT 105CSPBGA
產(chǎn)品變化通告: AD9992 Discontinuation 22/Feb/2012
標(biāo)準(zhǔn)包裝: 2,000
類型: CCD 信號處理器,12 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
電流 - 電源: 27mA
安裝類型: 表面貼裝
封裝/外殼: 105-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 105-CSPBGA(8x8)
包裝: 帶卷 (TR)
AD9992
Rev. C | Page 59 of 92
VD
HD
SUSPEND
SYNC
73
5
NOTES
1. THE SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO 0.
2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13).
3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x13).
4. THE SYNC RISING EDGE CAUSES THE INTERNAL FIELD DESIGNATOR TO INCREMENT.
5. IF SYNCSUSPEND = 1, VERTICAL CLOCKS, H1 TO H4, AND RG ARE HELD AT THE SAME POLARITY SPECIFIED BY OUTCONTROL = LOW.
6. IF SYNCSUSPEND = 0, ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL SYNC RESET EDGE.
FIELD
DESIGNATOR
H1 TO H4, RG,
XV1 TO XV24
VSG, SUBCK
0
58
91
-08
3
Figure 66. Default Mode 1
5
1
2
3
4
1FALLING EDGE RESYNCS THE CIRCUIT TO THE LINE/PIXEL NUMBER 0. VD AND HD INTERNALLY RESYNC.
2RISING EDGE RESETS COUNTERS.
3VD IS DISABLED DURING SYNC. THE REGISTER IS PROGRAMMABLE.
4SCP, HBLK, AND CLPOB ARE HELD AT SEQ0 VALUE.
5XV1 TO XV24 SIGNALS ARE HELD AT THE V-OUTPUT START POLARITY.
SYNC
VD
VDLEN
HD
SCP
XV1 TO XV24
0
5891-
084
Figure 67. Enhanced SYNC Mode 2 with Vertical Signals Held at VTP Start Value
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