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參數資料
| 型號： | AD9992BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 16/92頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SGNL PROC 12BIT 105CSPBGA |
| 產品變化通告： | AD9992 Discontinuation 22/Feb/2012 |
| 標準包裝： | 2,000 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 27mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應商設備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9992
Rev. C | Page 23 of 92
Register
Length
Range
Description
HBLKALT_PAT2
3b
0 to 5 even repeat area
HBLK Mode 2, Odd Field Repeat Area 1 pattern.
HBLKALT_PAT3
3b
0 to 5 even repeat area
HBLK Mode 2, Odd Field Repeat Area 2 pattern.
HBLKALT_PAT4
3b
0 to 5 even repeat area
HBLK Mode 2, Odd Field Repeat Area 3 pattern.
HBLKALT_PAT5
3b
0 to 5 even repeat area
HBLK Mode 2, Odd Field Repeat Area 4 pattern.
HBLKALT_PAT6
3b
0 to 5 even repeat area
HBLK Mode 2, Odd Field Repeat Area 5 pattern.
HBLK
H-BLANK REPEATING PATTERN IS CREATED USING HBLKLEN AND HBLKREP REGISTERS
H1/H3
H2/H4
HBLKSTART
HBLKTOGE1
HBLKTOGE2
HBLKEND
HBLKTOGE3
HBLKTOGE4
HBLKLEN
HBLKREP NUMBER 1
HBLKREP NUMBER 2
HBLKREP NUMBER 3
HBLKREP = 3
05
89
1-
02
7
Figure 27. HBLK Repeating Pattern Using HBLKMODE = 1
HBLK Mode 1 Operation
Multiple repeats of the HBLK signal are enabled by setting
HBLKMODE to 1. In this mode, the HBLK pattern can be
generated using a different set of registers: HBLKSTART,
HBLKEND, HBLKLEN, and HBLKREP, along with the six
toggle positions (see Figure 27).
Separate toggle positions are available for even and odd lines. If
alternation is not needed, the same values should be loaded into
the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines.
Generating HBLK Line Alternation
HBLK Mode 0 and HBLK Mode 1 provide the ability to
alternate different HBLK toggle positions on even and odd
lines. HBLK line alternation can be used in conjunction with
V-pattern odd/even alternation or on its own. Separate toggle
positions are available for even and odd lines. If even/odd line
alternation is not required, the same values should be loaded into
the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines.
Increasing H-Clock Width During HBLK
HBLK Mode 0 and HBLK Mode 1 allow the H1 to H8 pulse
widths to be increased during the HBLK interval. As shown in
Figure 28, the H-clock frequency can be reduced by a factor of
1/2, 1/4, 1/6, 1/8, 1/10, 1/12, and so on, up to 1/30. To enable
this feature, the HCLK_WIDTH register (Address 0x34,
Bits [7:4]) is set to a value between 1 and 15. When this register
is set to 0, the wide HCLK feature is disabled. The reduced
frequency occurs only for H1 to H8 pulses that are located
within the HBLK area.
The HCLK_WIDTH register is generally used in conjunction
with special HBLK patterns to generate vertical and horizontal
mixing in the CCD.
Note that the wide HCLK feature is available only in HBLK
Mode 0 and HBLK Mode 1. HBLK Mode 2 does not support
wide HCLKs.
Table 12. HCLK Width Register
Register
Length
Description
HCLK_WIDTH
4b
Controls H1 to H8 pulse widths
during HBLK as a fraction of pixel rate
0: Same frequency as pixel rate
1: 1/2 pixel frequency, that is, doubles
the HCLK pulse width
2: 1/4 pixel frequency
3: 1/6 pixel frequency
4: 1/8 pixel frequency
5: 1/10 pixel frequency
…
15: 1/30 pixel frequency
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相關代理商/技術參數 |
參數描述 |
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| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應商器件封裝:196-CSPBGA（12x12） 標準包裝:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應商器件封裝:196-CSPBGA（12x12） 標準包裝:1,500 |
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