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| 型號： | AD9992BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SGNL PROC 12BIT 105CSPBGA |
| 產(chǎn)品變化通告： | AD9992 Discontinuation 22/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 27mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9992
Rev. C | Page 41 of 92
Multiplier Mode
To generate very wide vertical timing pulses, a vertical region
can be configured into a multiplier region. This mode uses
the V-pattern registers in a slightly different manner. Multiplier
mode can be used to support unusual CCD timing requirements,
such as vertical pulses that are wider than the 13-bit V-pattern
toggle position counter. In general, the 13-bit toggle position
counter can be used with the sweep mode feature to support very
wide pulses; however, multiplier mode can be used to generate
even wider pulses.
The start polarity and toggle positions are still used in the same
manner as the standard V-pattern group programming, but
VLEN is used differently. Instead of using the pixel counter
(HD counter) to specify the toggle position locations (XVTOG1,
XVTOG2, XVTOG3, and XVTOG4) of the V-pattern group,
the VLEN is multiplied with the XVVTOG position to allow
very long pulses to be generated. To calculate the exact toggle
position, which is counted in pixels after the start position, use the
following equation:
Multiplier Mode Toggle Position = XVTOG × VLEN
Because the XVTOG register is multiplied by VLEN, the
resolution of the toggle position placement is reduced. If VLEN =
4, the toggle position precision is reduced to 4-pixel increments
instead of to single-pixel increments. Table 18 summarizes how
the V-pattern group registers are used in multiplier mode
operation. In multiplier mode, the VREP registers must always be
programmed to the same value as the highest toggle position.
Figure 50 illustrates this operation. The first toggle position is 2,
and the second toggle position is 9. In nonmultiplier mode, this
causes the V-sequence to toggle at Pixel 2 and then at Pixel 9 within
a single HD line. However, in multiplier mode, toggle positions are
multiplied by the value of VLEN (in this case, 4); therefore, the first
toggle occurs at Pixel 8, and the second toggle occurs at Pixel 36.
Sweep mode has also been enabled to allow the toggle positions
to cross the HD line boundaries.
Table 18. Multiplier Mode Register Parameters
Register
Length
Range
Description
MULTI
1b
High/low
High enables multiplier mode.
VPOL
1b
High/low
Starting polarity of XV1 to XV10 signals in each V-pattern group.
XVTOG
13b
0 to 8191 pixel location
Toggle positions for XV1 to XV10 signals in each V-pattern group.
VLEN
13b
0 to 8191 pixels
Used as multiplier factor for toggle position counter.
VREP
13b
0 to 8191 pixel location
VREP_EVEN/VREP_ODD must be set to the same value as the highest XVTOG value.
XV1 TO XV10
HD
VLEN
12 3412 341 2341 2341 2341 234 1234 1234 123 4123 4
START POSITION OF VPAT GROUP IS STILL PROGRAMMED IN THE V-SEQUENCE REGISTERS
PIXEL
NUMBER
12 3456 789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
3
55
4
1
2
4
2
05
89
1-
05
0
MULTIPLIER MODE V-PATTERN GROUP PROPERTIES:
1START POLARITY (STARTPOL = 0).
2FIRST, SECOND, AND THIRD TOGGLE POSITIONS (XVTOG1 = 2, XVTOG2 = 9).
3LENGTH OF VPAT COUNTER (VLEN = 4); THIS IS THE MINIMUM RESOLUTION FOR TOGGLE POSITION CHANGES.
4TOGGLE POSITIONS OCCUR AT LOCATION EQUAL TO (XVTOG × VLEN).
5IF SWEEP REGION IS ENABLED, THE V-PULSES MAY ALSO CROSS THE HD BOUNDRIES, AS SHOWN ABOVE.
Figure 50. Example of Multiplier Region for Wide Vertical Pulse Timing
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| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1 |
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