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| 型號： | AD9992BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 52/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SGNL PROC 12BIT 105CSPBGA |
| 產(chǎn)品變化通告： | AD9992 Discontinuation 22/Feb/2012 |
| 標準包裝： | 2,000 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 27mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9992
Rev. C | Page 56 of 92
COMPLETE EXPOSURE/READOUT OPERATION
USING PRIMARY COUNTER AND GPO SIGNALS
Figure 65 demonstrates a typical expose/read cycle while exercising
the GPO signals. Using a 3-field CCD with an exposure time
that is greater than one field but less than two fields in duration
requires a total of five fields for the entire exposure/readout
operation. Other exposure times and other CCD field config-
urations require modification of these example settings.
Note that, if the MODE registers are changed to VD updated, as
shown in the MODE Registers section and in Figure 53, the
MODE update is delayed by one additional field. This should be
accounted for in selecting the number of fields to cycle and the VD
location to write to the MODE registers.
1.
The primary counter is used to control the masking of VSG
and SUBCK during exposure/readout. The PRIMARY_MAX
register should be set equal to the total number of fields
used for exposure and readout. In this example,
PRIMARY_MAX = 5.
The SUBCK masking should not occur immediately at
the next VD edge (Step 2) because this would define an
exposure time that begins in the previous field. Write to
the PRIMARY_DELAY register to delay the masking of
VSG and SUBCK pulses in the first exposure field. In this
example, MASKDELAY = 1.
Write to the SUBCKMASK_NUM register (Address 0x74)
to specify the number of fields to mask SUBCK while the
CCD data is read. In this example, SUBCKMASK_NUM = 4.
Write to the SGMASK_NUM register (Address 0x74) to
specify the number of fields to mask VSG outputs during
exposure. In this example, SGMASK_NUM = 1.
Write to the PRIMARY_ACTION register (Address 0x70)
to trigger the GP1 (STROBE), GP2 (MSHUT), and GP3
(VSUB) signals and to start the expose/read operation.
Write to the MODE registers to configure the next five
fields. The first two fields during exposure are the same as
the current draft mode fields, and the following three fields
are the still-frame readout fields. The register settings for
the draft mode field and the three readout fields are
previously programmed. Note that if the MODE registers
are changed to VD updated, only one field of exposure
should be included (the second one) because the MODE
settings will be delayed an extra field.
2.
VD/HD falling edge updates the serial writes from 1.
3.
GP3 (VSUB) output turns on at the field/line/pixel specified.
VSUB Example 1 and Example 2 use GP3TOG1_FD = 1.
4.
GP1 (STROBE) output turns on and off at the location
specified.
5.
GP2 (MSHUT) output turns off at the location specified.
6.
The next VD falling edge automatically starts the first
read field.
7.
The next VD falling edge automatically starts the second
read field.
8.
The next VD falling edge automatically starts the third
read field.
9.
Write to the MODE register to reconfigure the single draft
mode field timing. Note that if the MODE registers are
changed to VD updated, this write should occur one field
earlier.
10. VD/HD falling edge updates the serial writes from Step 9.
VSG outputs return to draft mode timing. SUBCK output
resumes operation. GP2 (MSHUT) output returns to the on
position (active or open). GP3 (VSUB) output returns to
the off position (inactive)
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| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應商器件封裝:196-CSPBGA（12x12） 標準包裝:1,500 |
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